Temat: SOI - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Grain boundary effect on the anisotropy piezoresistance of laser-recrystallized polysilicon layers in SOI-structures
Autorzy:: Pankov, Y.
Druzhinin, A.
Powiązania:: https://bibliotekanauki.pl/articles/307640.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI
polysilicon layers
MLR
Opis:: A physical model of grain boundary influence on the piezoresistive effect of p-type conductivity of polysilicon layers in SOI-structures is developed. Software calculating piezoresistive properties of boron-doped p-type polysilicon layers has been developed. These properties may be calculated over wide concentration and temperature ranges with anisotropy taken into account and with the average grain size as a parameter. The potential barrier regions around the grain boundaries influence the deformation changes of anisotropy resistance in the fine-grained non-recrystallized SOI-structures doped with boron up to 3ź10(19)cm(-3) only.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 46-48
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Recent developments in vertical MOSFETs and SiGe HBTs
Autorzy:: Hall, S.
Buiu, O.
Ashburn, P.
de Groot, K.
Powiązania:: https://bibliotekanauki.pl/articles/308031.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: vertical MOSFET
HBT
SOI
Opis:: There is a well recognised need to introduce new materials and device architectures to Si technology to achieve the objectives set by the international roadmap. This paper summarises our work in two areas: vertical MOSFETs, which can allow increased current drive per unit area of Si chip and SiGe HBT's in silicon-on-insulator technology, which bring together and promise to extend the very high frequency performance of SiGe HBT's with SOI-CMOS.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 26-35
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Characterization of SOI fabrication process using gated-diode measurements and TEM studies
Autorzy:: Gibki, J.
Kątcki, J.
Ratajczak, J.
Łukasik, L.
Jakubowski, A.
Tomaszewski, D.
Powiązania:: https://bibliotekanauki.pl/articles/309219.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
SOI technology
characterization
Opis:: SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 81-83
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Traduire l'expression «soi-disant» en polonais: le cas des copies d'étudiants
Translation of the expression soi-disant into Polish: a case of students calques
Autorzy:: Dutka-Mańkowska, Anna
Powiązania:: https://bibliotekanauki.pl/articles/1053091.pdf
Data publikacji:: 2003-10-01
Wydawca:: Uniwersytet im. Adama Mickiewicza w Poznaniu
Tematy:: Expression "soi-disant"
Translation
Opis:: Students' translations into Polish of the French expression soi disant (found in the "Frantext" programme) are considered on two Ievels: that of linguistic means used (modalisers, antonymous modality, apparent reported speech, verb expressions of the type: vouloir/paraitre/passer pour and ways of quoting another discourse (possibility of using explicite/implicite). The semantic and contrastive approach appears to be useful in the description of Polish words (e.g. niejako), particularly difficult from the point of view of the theory of combinations.Translation
Źródło:: Studia Romanica Posnaniensia; 2003, 30; 41-49
0137-2475
2084-4158
Pojawia się w:: Studia Romanica Posnaniensia
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Silicon microelectronics: where we have come from and where we are heading
Autorzy:: Łukasiak, L.
Jakubowski, A.
Pióro, Z.
Powiązania:: https://bibliotekanauki.pl/articles/308029.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: MOSFET
scaling
SiGe
SOI
Opis:: The paper briefly presents the history of microelectronics and the limitations of its further progress, as well as possible solutions. The discussion includes the consequences of the reduction of gate-stack capacitance and difficulties associated with supply-voltage scaling, minimization of parasitic resistance, increased channel doping and small size. Novel device architectures (e.g. SON, double-gate transistor) and the advantages of silicon-germanium are considered, too.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 7-14
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Wymagania dla środków ochrony indywidualnej (SOI) w górnictwie podziemnym
Autorzy:: Lipowczan, A.
Powiązania:: https://bibliotekanauki.pl/articles/370737.pdf
Data publikacji:: 2009
Wydawca:: Wyższa Szkoła Zarządzania Ochroną Pracy w Katowicach
Tematy:: sprzęt ochrony indywidualnej
SOI
klasyfikacja SOI
wybuchowe środowisko pracy
parametry antropometryczne SOI
uniwersalność SOI
personal individualprotector
PIP
classification of PIP
explosives conditions in work environment
anthropometric factors
PIP universality
Opis:: W referacie przedstawiono czynniki determinujące znaczenie stosowania środków ochrony indywidualnej w górnictwie ze szczególnym uwzględnieniem górnictwa podziemnego. Przytoczono klasyfikację SOI. Na tej podstawie omówiono uwarunkowania certy-fikacyjne wynikające z wymagań Unii Europejskiej oraz przedstawiono trzy istotne czynniki charakterystyczne dla górnictwa, które powinny być uwzględniane w procesie wyboru SOI.
The paper presents the importance of personal individual protector (PIP) factors in mining industry with the special stress on coal underground mining. The classification of PIP was quoted in the paper. On these bases the certification conditions which arise from EU directives are also presented. In author opinion there are three main factors which are representative for mining industry and must be taken into account during the selection processes i.e.: explosives conditions in work environment, anthropometric factors of protected population and PIP universality.
Źródło:: Zeszyty Naukowe Wyższej Szkoły Zarządzania Ochroną Pracy w Katowicach; 2009, 1(5); 5-13
1895-3794
2300-0376
Pojawia się w:: Zeszyty Naukowe Wyższej Szkoły Zarządzania Ochroną Pracy w Katowicach
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 7.

Tytuł:: Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs
Autorzy:: Goffioul, M.
Vanhoenacker, D.
Raskin, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/309316.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
microwave devices
SOI MOSFET
Opis:: Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 59-66
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 8.

Tytuł:: Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs
Autorzy:: Goffioul, M.
Dambrine, G.
Vanhoenacker, D.
Raskin, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/309323.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
microwave devices
SOI MOSFET
Opis:: The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 72-80
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 9.

Tytuł:: Silicon-on-Insulator technology for imaging and application to a switching photodetector
Autorzy:: Abdo, N.
Sallin, D.
Koukab, A.
Estribeau, M.
Magnan, P.
Kayal, M.
Powiązania:: https://bibliotekanauki.pl/articles/397865.pdf
Data publikacji:: 2015
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: photodetectors
silicon-on-insulator
fotodetektory
SOI
Opis:: This paper analyzes some advantages of Silicon-on-Insulator (SOI) based photodetectors for low light imaging. It shows that SOI based sensors not only solve the bulk carriers problem, it can also act as a very selective spectral filter by acting as a resonant cavity, which is useful in application with a very narrow spectrum of interest, such as bioluminescence imaging. The SOI implementation of a switching photodetector based with an hybrid MOS-PN structure is presented and its advantages in terms of dark current minimization and SNR improvement highlighted.
Źródło:: International Journal of Microelectronics and Computer Science; 2015, 6, 4; 136-141
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 10.

Tytuł:: Scattering mechanisms in MOS/SOI devices with ultrathin semiconductor layers
Autorzy:: Walczak, J.
Majkusiak, B.
Powiązania:: https://bibliotekanauki.pl/articles/308021.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: ultrathin SOI
scattering mechanisms
electron mobility
Opis:: Main scattering mechanisms affecting electron transport in MOS/SOI devices are considered within the quantum-mechanical approach. Electron mobility components (i.e., phonon, Coulomb and interface roughness limited mobilities) are calculated for ultrathin symmetrical DG SOI transistor, employing the relaxation time approximation, and the effective electron mobility is obtained showing possible mobility increase relative to the conventional MOSFET in the range of the active semiconductor layer thickness of about 3 nm.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 39-49
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 11.

Tytuł:: On possibility to extend the operation temperature range of SOI sensors with polysilicon piezoresistors
Autorzy:: Druzhinin, A.
Lavitska, E.
Maryamova, I.
Kogut, I.
Khoverko, Y.
Powiązania:: https://bibliotekanauki.pl/articles/307642.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI
mechanical sensors
poly-Si piezoresistor
ZMR
Opis:: The aim of this work was to study the possibilities of developing mechanical sensors with poly-Si piezoresistors on insulating substrate for operation in different temperature ranges (low, elevated and high temperatures). Laser recrystallization is used as a technological tool to adjust the electrical and piezoresistive parameters of the polysilicon layer. For this purpose a set of studies including numerical simulation and experimental work has been carried out. The main three directions of the studies are considered: problems of thermal stabilization of the pressure sensor performance at elevated and high temperatures; problem of sensor operation at cryogenic temperatures; development of a multifunctional pressure-temperature sensor.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 40-45
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 12.

Tytuł:: TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology
Autorzy:: Barański, M.
Domański, K.
Grabiec, P.
Grodner, M.
Jaroszewicz, B.
Kociubiński, A.
Kucewicz, W.
Kucharski, K.
Marczewski, J.
Niemiec, H.
Sapor, M.
Tomaszewski, D.
Powiązania:: https://bibliotekanauki.pl/articles/308825.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI CMOS technology
pixel detector
test structure
Opis:: This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-_lm SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 85-93
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 13.

Tytuł:: High-temperature instability processes in SOI structures and MOSFETs
Autorzy:: Nazarov, A.N.
Kilchytska, V.I.
Vovk, Ja.N.
Colinge, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/307654.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI
MOSFET
high-temperature
instability
ZMR
SIMOX
Opis:: The paper reviews the problems related to BOX high-temperature instability in SOI structures and MOSFETs. The methods of bias-temperature research applied to SOI structures and SOI MOSFETs are analysed and the results of combined electrical studies of ZMR, and SIMOX SOI structures are presented. The studies are focused mainly on electrical discharging processes in the BOX at high temperature and its link with new instability phenomena such as high-temperature kink effects in SOI MOSFETs.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 18-26
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 14.

Tytuł:: A model of partially-depleted SOI MOSFETs in the subthreshold range
Autorzy:: Tomaszewski, D.
Łukasiak, L.
Jakubowski, A.
Domański, K.
Powiązania:: https://bibliotekanauki.pl/articles/308425.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
subthreshold range
floating body
transconductance
Opis:: A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in current continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion-based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the "pinch-off" region and avalanche multiplication triggered by these carriers. Characteristics of the presented model are shown and briefly discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 61-64
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 15.

Tytuł:: Standardization of the compact model coding: non-fully depleted SOI MOSFET example
Autorzy:: Grabiński, W.
Tomaszewski, D.
Lemaitre, L.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/308862.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: Verilog-AMS
compact model coding
SOI MOSFET
Opis:: The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 135-141
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 16.

Tytuł:: CMOS Readout Circuit Integrated with Ionizing Radiation Detectors
Autorzy:: Szymański, A.
Obrębski, D.
Marczewski, J.
Tomaszewski, D.
Grodner, M.
Pieczyński, J.
Powiązania:: https://bibliotekanauki.pl/articles/226502.pdf
Data publikacji:: 2014
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: readout electronics
ASIC
SOI
ionizing radiation detectors
Opis:: This paper describes the work performed in ITE on integration in one CMOS chip the ionizing radiation detectors with dedicated readout electronics. At the beginning, some realizations of silicon detectors of ionizing radiation are presented together with most important issues related to these devices. Next, two developed test structures for readout electronics are discussed in detail together with main features of non-typical silicon proces deployed.
Źródło:: International Journal of Electronics and Telecommunications; 2014, 60, 1; 117-124
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 17.

Tytuł:: Reliability of deep submicron MOSFETs
Autorzy:: Balestra, F.
Powiązania:: https://bibliotekanauki.pl/articles/307658.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: bulk MOSFETs
SOI devices
deep submicron
transistors
reliability
Opis:: In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradation are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, defice lifetime and maximum drain bias that can be applied are addressed. The physical mechanisms and the emergence of new phenomena at the origin of the degradation are studied for advanced MOS transistors. The impact of the substrate bias is also outlined.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 12-17
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 18.

Tytuł:: High-voltage SoI Unity-gain Voltage Buffers with Function-enable and Power-down Functionality
Autorzy:: Jankowski, M
Napieralski, A
Powiązania:: https://bibliotekanauki.pl/articles/397893.pdf
Data publikacji:: 2013
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: wysokonapięciowy układ scalony
proces SoI
stan wysokiej impedancji
high-voltage integrated circuits
SoI process
high impedance state
enable functionality
Opis:: This paper discusses possibilities of enable and power-down functionality implementation in HV SoI unity-gain buffers. Modifications of selected HV buffer structures are analyzed. Approaches of power-down, high input and output impedance functionality implementation are introduced and discussed.
Źródło:: International Journal of Microelectronics and Computer Science; 2013, 4, 1; 26-31
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 19.

Tytuł:: Characterization of SOI MOSFETs by means of charge-pumping
Autorzy:: Głuszko, G.
Szostak, S.
Gottlob, H.
Lemme, M.
Łukasiak, L.
Powiązania:: https://bibliotekanauki.pl/articles/308671.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: charge-pumping
electrical characterization
interface traps
SOI MOSFET
Opis:: This paper presents the results of charge-pumping measurements of SOI MOSFETs. The aim of these measurements is to provide information on the density of interface traps at the front and back Si-SiO2 interface. Three-level charge-pumping is used to obtain energy distribution of interface traps at front-interface.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 67-72
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 20.

Tytuł:: Trends in hybrid pixel detectors for X-ray imaging using deep submicron VLSI technology
Autorzy:: Drozd, A.
Satława, T.
Powiązania:: https://bibliotekanauki.pl/articles/115661.pdf
Data publikacji:: 2014
Wydawca:: Fundacja na Rzecz Młodych Naukowców
Tematy:: X-ray imaging
hybrid pixel detectors
3D technologies
SOI technologies
obrazowanie rentgenowskie
hybrydowe detektory pikseli
technologie 3D
technologia SOI
Opis:: The article covers the latest developments in pixel detectors used for X-ray imaging as well as the description of the practical solution – a multichannel integrated circuit dedicated to X-ray imaging. In general introduction a wide range of pixel detector applications is presented. The main part focuses on the challenges and new solutions for the field of X-ray imaging, including 3D integration, silicon-on-insulator and submicron technologies. Since minimization of a pixel size together with implementing more functionality are important issues in the detectors’ and integrated circuits’ design, the aspects of channel-to-channel uniformity and additional effects like charge sharing between pixels are taken into consideration. In the last section, the Authors present the application specific integrated circuit designed in 40 nm technology dedicated to X-ray detection and future prospects are discussed.
Źródło:: Challenges of Modern Technology; 2014, 5, 4; 3-7
2082-2863
2353-4419
Pojawia się w:: Challenges of Modern Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 21.

Tytuł:: Montaigne : l’écriture de soi pour penser l’altérité
Montaigne: Writing and Thinking the Other from the Self
Autorzy:: Buchs, Arnaud
Powiązania:: https://bibliotekanauki.pl/articles/2056745.pdf
Data publikacji:: 2021
Wydawca:: Uniwersytet Marii Curie-Skłodowskiej. Wydawnictwo Uniwersytetu Marii Curie-Skłodowskiej
Tematy:: Montaigne
essais
otherness
writing
self
Essais
altérité
écriture
soi
Opis:: Le souci de l’autre, chez Montaigne, est constant, les figures de l’altérité sont d’une extraordinaire richesse. Et pourtant, Montaigne est surtout connu pour être l’écrivain de soi. Mais le « soy » de Montaigne, comme le Journal de voyage et les Essais, est en fait traversé par l’altérité. Cet article vise alors à montrer comment Montaigne, en particulier dans les Essais, va écrire puis penser l’autre à partir de soi.
Concern for the other is constant with Montaigne, the figures of otherness are extraordinarily rich. And yet, Montaigne is known above all as the writer of the self. But the “soy” of Montaigne, like the Journal de voyage and the Essais, is in fact saturated by otherness. This article aims therefore to show how Montaigne, in particular in the Essais, will write and imagine the other from the self.
Źródło:: Lublin Studies in Modern Languages and Literature; 2021, 45, 4; 5-13
0137-4699
Pojawia się w:: Lublin Studies in Modern Languages and Literature
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 22.

Tytuł:: Raconter des histoires pour développer des compétences transversales en FLE
Tell stories to develop transversal competencies in FLE
Autorzy:: Blachowska-Szmigiel, Marzena
Powiązania:: https://bibliotekanauki.pl/articles/1048268.pdf
Data publikacji:: 2019-07-09
Wydawca:: Uniwersytet im. Adama Mickiewicza w Poznaniu
Tematy:: transversal competencies
narrative competence
‘SOI’ integrity
FLE teaching / learning
Opis:: The purpose of this paper is to seek to highlight the usefulness of storytelling skills for the development of transversal competencies in the context of FLE teaching / learning in Romance philology at Adam Mickiewicz University. As a first step we define the importance of transversal competencies in developing the general communicative competence of the student as a participant in social life, then we go on to describe narrative competence as transversal competence and to show its role in managing the ‘SOI’ integrity, finally, we concentrate on developing narrative competence on Roman philology at Adam Mickiewicz University.
Źródło:: Studia Romanica Posnaniensia; 2019, 46, 2; 99-110
0137-2475
2084-4158
Pojawia się w:: Studia Romanica Posnaniensia
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 23.

Tytuł:: Capacitance/Resistance Modeling and Analog Performance Evaluation of 3-D SOI FinFET Structure for Circuit Perspective Applications
Autorzy:: Jain, Neeraj
Raj, Balwinder
Powiązania:: https://bibliotekanauki.pl/articles/1159723.pdf
Data publikacji:: 2018
Wydawca:: Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Tematy:: CMOS
Integrated Circuits
Parasitic Capacitance
Parasitic Resistance
SOI FinFET
Opis:: This paper explores the capacitance and resistance modeling of 3-D (dimensional) SOI FinFET structure and circuit implementation approach is done for the utility of SOI FinFET structure. The scaling of the FinFET structure is continuously ongoing and increased parasitic and resistance affects the circuit level performance of SOI FinFET in ICs (Integrated Circuits) below 20 nm technology node. A geometrical-based analysis is done to get the optimized parasitic capacitance and resistance model and validity of the model is verified by three-dimensional (3-D) field solver Synopsys Raphael software. For utility of the developed model, some circuit implementation is done in h-spice simulation environment.
Źródło:: World Scientific News; 2018, 113; 194-209
2392-2192
Pojawia się w:: World Scientific News
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 24.

Tytuł:: An impact of frequency on capacitances of partially-depleted SOI MOSFETs
Autorzy:: Tomaszewski, D.
Łukasik, L.
Zaręba, A.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/309325.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
small-signal models
non-quasi-static analysis
admittances
Opis:: A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 67-71
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 25.

Tytuł:: Measurement and performance evaluation of a silicon on insulator pixel matrix
Autorzy:: Ntavelis, D.
Harik, L.
Sallese, J.-M.
Kayal, M.
Hatzopoulos, A.
Powiązania:: https://bibliotekanauki.pl/articles/397821.pdf
Data publikacji:: 2010
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: technika SOI tranzystora polowego MOS
czujnik obrazu
pompować ładunek
pierwsza kolejność delta-sigma
SOI MOSFET
image sensors
charge pumping
first order delta-sigma
Opis:: A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.
Źródło:: International Journal of Microelectronics and Computer Science; 2010, 1, 3; 299-304
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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