Temat: SOI - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Grain boundary effect on the anisotropy piezoresistance of laser-recrystallized polysilicon layers in SOI-structures
Autorzy:: Pankov, Y.
Druzhinin, A.
Powiązania:: https://bibliotekanauki.pl/articles/307640.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI
polysilicon layers
MLR
Opis:: A physical model of grain boundary influence on the piezoresistive effect of p-type conductivity of polysilicon layers in SOI-structures is developed. Software calculating piezoresistive properties of boron-doped p-type polysilicon layers has been developed. These properties may be calculated over wide concentration and temperature ranges with anisotropy taken into account and with the average grain size as a parameter. The potential barrier regions around the grain boundaries influence the deformation changes of anisotropy resistance in the fine-grained non-recrystallized SOI-structures doped with boron up to 3ź10(19)cm(-3) only.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 46-48
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Recent developments in vertical MOSFETs and SiGe HBTs
Autorzy:: Hall, S.
Buiu, O.
Ashburn, P.
de Groot, K.
Powiązania:: https://bibliotekanauki.pl/articles/308031.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: vertical MOSFET
HBT
SOI
Opis:: There is a well recognised need to introduce new materials and device architectures to Si technology to achieve the objectives set by the international roadmap. This paper summarises our work in two areas: vertical MOSFETs, which can allow increased current drive per unit area of Si chip and SiGe HBT's in silicon-on-insulator technology, which bring together and promise to extend the very high frequency performance of SiGe HBT's with SOI-CMOS.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 26-35
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Characterization of SOI fabrication process using gated-diode measurements and TEM studies
Autorzy:: Gibki, J.
Kątcki, J.
Ratajczak, J.
Łukasik, L.
Jakubowski, A.
Tomaszewski, D.
Powiązania:: https://bibliotekanauki.pl/articles/309219.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
SOI technology
characterization
Opis:: SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 81-83
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Silicon microelectronics: where we have come from and where we are heading
Autorzy:: Łukasiak, L.
Jakubowski, A.
Pióro, Z.
Powiązania:: https://bibliotekanauki.pl/articles/308029.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: MOSFET
scaling
SiGe
SOI
Opis:: The paper briefly presents the history of microelectronics and the limitations of its further progress, as well as possible solutions. The discussion includes the consequences of the reduction of gate-stack capacitance and difficulties associated with supply-voltage scaling, minimization of parasitic resistance, increased channel doping and small size. Novel device architectures (e.g. SON, double-gate transistor) and the advantages of silicon-germanium are considered, too.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 7-14
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs
Autorzy:: Goffioul, M.
Vanhoenacker, D.
Raskin, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/309316.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
microwave devices
SOI MOSFET
Opis:: Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 59-66
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs
Autorzy:: Goffioul, M.
Dambrine, G.
Vanhoenacker, D.
Raskin, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/309323.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
microwave devices
SOI MOSFET
Opis:: The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 72-80
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 7.

Tytuł:: Scattering mechanisms in MOS/SOI devices with ultrathin semiconductor layers
Autorzy:: Walczak, J.
Majkusiak, B.
Powiązania:: https://bibliotekanauki.pl/articles/308021.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: ultrathin SOI
scattering mechanisms
electron mobility
Opis:: Main scattering mechanisms affecting electron transport in MOS/SOI devices are considered within the quantum-mechanical approach. Electron mobility components (i.e., phonon, Coulomb and interface roughness limited mobilities) are calculated for ultrathin symmetrical DG SOI transistor, employing the relaxation time approximation, and the effective electron mobility is obtained showing possible mobility increase relative to the conventional MOSFET in the range of the active semiconductor layer thickness of about 3 nm.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 39-49
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 8.

Tytuł:: On possibility to extend the operation temperature range of SOI sensors with polysilicon piezoresistors
Autorzy:: Druzhinin, A.
Lavitska, E.
Maryamova, I.
Kogut, I.
Khoverko, Y.
Powiązania:: https://bibliotekanauki.pl/articles/307642.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI
mechanical sensors
poly-Si piezoresistor
ZMR
Opis:: The aim of this work was to study the possibilities of developing mechanical sensors with poly-Si piezoresistors on insulating substrate for operation in different temperature ranges (low, elevated and high temperatures). Laser recrystallization is used as a technological tool to adjust the electrical and piezoresistive parameters of the polysilicon layer. For this purpose a set of studies including numerical simulation and experimental work has been carried out. The main three directions of the studies are considered: problems of thermal stabilization of the pressure sensor performance at elevated and high temperatures; problem of sensor operation at cryogenic temperatures; development of a multifunctional pressure-temperature sensor.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 40-45
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 9.

Tytuł:: TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology
Autorzy:: Barański, M.
Domański, K.
Grabiec, P.
Grodner, M.
Jaroszewicz, B.
Kociubiński, A.
Kucewicz, W.
Kucharski, K.
Marczewski, J.
Niemiec, H.
Sapor, M.
Tomaszewski, D.
Powiązania:: https://bibliotekanauki.pl/articles/308825.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI CMOS technology
pixel detector
test structure
Opis:: This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-_lm SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 85-93
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 10.

Tytuł:: High-temperature instability processes in SOI structures and MOSFETs
Autorzy:: Nazarov, A.N.
Kilchytska, V.I.
Vovk, Ja.N.
Colinge, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/307654.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI
MOSFET
high-temperature
instability
ZMR
SIMOX
Opis:: The paper reviews the problems related to BOX high-temperature instability in SOI structures and MOSFETs. The methods of bias-temperature research applied to SOI structures and SOI MOSFETs are analysed and the results of combined electrical studies of ZMR, and SIMOX SOI structures are presented. The studies are focused mainly on electrical discharging processes in the BOX at high temperature and its link with new instability phenomena such as high-temperature kink effects in SOI MOSFETs.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 18-26
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 11.

Tytuł:: A model of partially-depleted SOI MOSFETs in the subthreshold range
Autorzy:: Tomaszewski, D.
Łukasiak, L.
Jakubowski, A.
Domański, K.
Powiązania:: https://bibliotekanauki.pl/articles/308425.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
subthreshold range
floating body
transconductance
Opis:: A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in current continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion-based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the "pinch-off" region and avalanche multiplication triggered by these carriers. Characteristics of the presented model are shown and briefly discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 61-64
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 12.

Tytuł:: Standardization of the compact model coding: non-fully depleted SOI MOSFET example
Autorzy:: Grabiński, W.
Tomaszewski, D.
Lemaitre, L.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/308862.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: Verilog-AMS
compact model coding
SOI MOSFET
Opis:: The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 135-141
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 13.

Tytuł:: Reliability of deep submicron MOSFETs
Autorzy:: Balestra, F.
Powiązania:: https://bibliotekanauki.pl/articles/307658.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: bulk MOSFETs
SOI devices
deep submicron
transistors
reliability
Opis:: In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradation are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, defice lifetime and maximum drain bias that can be applied are addressed. The physical mechanisms and the emergence of new phenomena at the origin of the degradation are studied for advanced MOS transistors. The impact of the substrate bias is also outlined.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 12-17
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 14.

Tytuł:: Characterization of SOI MOSFETs by means of charge-pumping
Autorzy:: Głuszko, G.
Szostak, S.
Gottlob, H.
Lemme, M.
Łukasiak, L.
Powiązania:: https://bibliotekanauki.pl/articles/308671.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: charge-pumping
electrical characterization
interface traps
SOI MOSFET
Opis:: This paper presents the results of charge-pumping measurements of SOI MOSFETs. The aim of these measurements is to provide information on the density of interface traps at the front and back Si-SiO2 interface. Three-level charge-pumping is used to obtain energy distribution of interface traps at front-interface.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 67-72
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 15.

Tytuł:: An impact of frequency on capacitances of partially-depleted SOI MOSFETs
Autorzy:: Tomaszewski, D.
Łukasik, L.
Zaręba, A.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/309325.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
small-signal models
non-quasi-static analysis
admittances
Opis:: A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 67-71
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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