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Wyszukujesz frazę "low-power consumption" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Design of broadband power line communication module for automatic meter reading
Autorzy:
Chen, Xia
Liu, Ling
Powiązania:
https://bibliotekanauki.pl/articles/949869.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
automatic meter reading
low-power consumption
long-distance transmission
power line communication
Opis:
Low-power consumption and long-distance transmission are two problems that have to be solved by the application of broadband power line communication for the automatic meter reading system. To reduce the power consumption of the communication module, based on the analysis of the composition of the power consumption, some methods are proposed. From the communication chip level and the module circuit level, the design scheme of low-power consumption is given. To solve the problem of transmission distance, a frequency band of 2.44 MHz~5.6 MHz is used as the main working frequency band. The communication module supports multiple frequency bands. Using this feature, the optimal frequency band is adaptively selected for communication and automatic switching, which further improve the transmission distance. Field application shows that the above methods effectively decrease the power consumption of the communication module and extend the transmission distance.
Źródło:
Archives of Electrical Engineering; 2020, 69, 4; 771-780
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low power BIST
Autorzy:
Puczko, M.
Powiązania:
https://bibliotekanauki.pl/articles/114375.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
low power
BIST
test pattern generator
signature analyzer
test-per-scan
test-per-clock
power consumption
Opis:
In the last years designers have mainly concentrated on low power consumption in mobile computing devices and cellular phones. In this paper, new solutions for reducing the switching activity of BIST environment for the scan-organized Built-In Self-Test (BIST) architectures is presented. The key idea behind this technique is based on the design of a new structure of LFSR to generate more than one pseudo random bit per one clock pulse. Theoretical calculations were hardware verified in two digital system design environments: WebPACK ISE by Xilinx and Quartus II by Altera. Power consumption measure tools were Xilinx XPower and Altera PowerPlay Power Analyzer Tool. The practical verification covers the power consumption of the Test Pattern Generator (TPG) as well as the complete BIST. The obtained results are over a dozen percent better compared to similar works.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 323-326
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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