Low power BIST

In the last years designers have mainly concentrated on low power consumption in mobile computing devices and cellular phones. In this paper, new solutions for reducing the switching activity of BIST environment for the scan-organized Built-In Self-Test (BIST) architectures is presented. The key idea behind this technique is based on the design of a new structure of LFSR to generate more than one pseudo random bit per one clock pulse. Theoretical calculations were hardware verified in two digital system design environments: WebPACK ISE by Xilinx and Quartus II by Altera. Power consumption measure tools were Xilinx XPower and Altera PowerPlay Power Analyzer Tool. The practical verification covers the power consumption of the Test Pattern Generator (TPG) as well as the complete BIST. The obtained results are over a dozen percent better compared to similar works.