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Tytuł:
A Low-Power Autonomous Sensor Module for Biomedical Applications
Autorzy:
Sondej, T.
Maciejewski, M.
Powiązania:
https://bibliotekanauki.pl/articles/114430.pdf
Data publikacji:
2016
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
low-power
sensor
biomedical application
Opis:
The paper presents the construction of an energy-efficient, stand-alone measurement module, designed for use in biomedical applications. The paper discusses the use of an algorithm implementing the acquisition and processing of data, whose main objective was to minimize energy consumption. For the construction of the measuring module, there are used a microcontroller with Cortex-M4F core and two external digital sensor systems: (1) analog-front-end circuit, designed to measure the ECG signal, and (2) a 3-axis system of an integrated accelerometer, gyroscope and magnetometer, made in MEMS technology. In order to minimize the energy consumption, the solutions proposed include dynamic frequency management, the introduction of sleep modes, and the use of selected hardware features of the microcontroller. The proposed techniques and algorithms are implemented to measure the ECG signal at a sampling rate of 250 Hz. Experimental studies of the sensor module constructed were carried out. As a result of the energy saving techniques used, the working time of the device was extended by more than 6 times.
Źródło:
Measurement Automation Monitoring; 2016, 62, 6; 206-208
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A - 5 dBm 400MHz OOK Transmitter for Wireless Medical Application
Autorzy:
Yousefi, M.
Koozehkanani, Z. D.
Jangi, H.
Nasirzadeh, N.
Sobhi, J.
Powiązania:
https://bibliotekanauki.pl/articles/226054.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
transmitter
power amplifier
on-off keying
low power
Opis:
A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at-5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.
Źródło:
International Journal of Electronics and Telecommunications; 2014, 60, 2; 193-198
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process
Autorzy:
Shylu Sam, D. S.
Sam Paul, P.
Jeba Jingle, Diana
Mano Paul, P.
Samuel, Judith
Reshma, J.
Sudeepa, P. Sarah
Evangeline, G.
Powiązania:
https://bibliotekanauki.pl/articles/2124770.pdf
Data publikacji:
2022
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
flash ADC
low power
dynamic comparator
encoder
Opis:
This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
Źródło:
International Journal of Electronics and Telecommunications; 2022, 68, 3; 565--570
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Modified Signal Feed-Through Pulsed Flip-Flop for Low Power Applications
Autorzy:
Panahifar, E.
Hassanzadeh, A.
Powiązania:
https://bibliotekanauki.pl/articles/226160.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
low power
pulsed flip-flop
delay
leakage power
dynamic power
Opis:
In this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 3; 241-246
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A 2.3-dB NF CMOS low voltage LNA optimized for medical applications at 600MHz
Autorzy:
Borrego, R
Powiązania:
https://bibliotekanauki.pl/articles/397807.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
DTMOS
balun
low voltage
low power
niskie napięcie
mała moc
Opis:
In this paper it is presented a balun LNA, with voltage gain control that combines a common-gate and common-source stage, in which transistors biased in triode region replace the resistive loads. This last approach in conjunction with a dynamic threshold reduction technique allows a low supply voltage operation. Furthermore, a significant chip area reduction can be exploited by adopting an inductor-less configuration. Simulations results with a 130 nm CMOS technology show that the gain is up to 19.3 dB and the NF is below 2.3 dB. The total dissipation is 4 mW, leading to an FOM of 2.26 for 0.6 V supply.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 3; 87-91
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Implementation of Bulk-Driven current differencing transconductance amplifier (BD-CDTA)
Autorzy:
Shaktour, M. A.
Powiązania:
https://bibliotekanauki.pl/articles/376266.pdf
Data publikacji:
2015
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
Bulk-Driven transistors
Low-voltage
Low-power CDTA
PSpice simulation
Opis:
This paper presents a new high performance Bulk-Driven current differencing transconductance amplifier (BD-CDTA), a recently reported active element, especially suitable for analog signal processing applications. The proposed BD-CDTA provides high output impedances at port Z and X, excellent input/output current tracking. The proposed BD-CDTA circuit operates at supply voltages of ± 0.6V. PSPICE simulation results using TSMC 0.18 μm CMOS process model are included to verify the expected values.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2015, 84; 145-151
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of Low Power Low Voltage Bulk Driven Operational Transconductance Amplifier (BD-OTA)
Autorzy:
Shaktour, M. A.
Powiązania:
https://bibliotekanauki.pl/articles/377604.pdf
Data publikacji:
2014
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
Bulk-driven transistors
low-voltage
low-power OTA
PSpice simulation
Opis:
Operational Transconductance Amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Here we design Low Power Low Voltage Bulk Driven OTA with a new concept of high-linearity OTA with controllable Transconductance is proposed. The OTA is simulated in a standard TSMC 0.18 mm CMOS process with a 0.6 V supply voltage.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 63-69
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FSM state merging for low power
Autorzy:
Salauyou, V.
Powiązania:
https://bibliotekanauki.pl/articles/114448.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
finite state machine
low power
merging
internal states
Opis:
A method of finite state machine (FSM) minimization for low power by merging FSM internal states is considered. The general algorithm for the minimization of FSM power consumption by means of merging two states is presented. The algorithm of the merging possibility of two states and the actual algorithm merging of two states for incompletely specified Mealy FSMs are given. In the conclusions, the possible directions of development of this approach are specified.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 337-339
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Intravascular low-power laser illumination through special fiber diffusers
Autorzy:
Bereś-Pawlik, E.
Derkacz, A.
Powiązania:
https://bibliotekanauki.pl/articles/200107.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
coronary angioplasty
restenosis
photostimulation
low-power laser radiation
Opis:
This paper presents the method of intravascular endothelial cell illumination with low-power laser radiation. Some special instruments were prepared, including designed fiber diffusers. The technical parameters of the set-up and the results of arterial system treatment with illumination instruments are presented.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2011, 59, 4; 441-443
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and Noise Analysis of a Novel Auto-Zeroing Structure for Continuous-Time Instrumentation Amplifiers
Autorzy:
Maréchal, S.
Nys, O.
Krummenacher, F.
Chevroulet, M.
Kayal, M.
Powiązania:
https://bibliotekanauki.pl/articles/226106.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
front-end
instrumentation amplifier
low-noise
low power
chopper
auto-zero
Opis:
This paper introduces a low-noise, low-power amplifier for high-impedance sensors. An innovative circuit using an auto-zeroed architecture combined with frequency modulation to reject offset and low-frequency noise is proposed and analysed. Special care was given to avoid broadband noise aliasing and chopping in the signal path, and to minimize both the resulting equivalent input offset voltage and equivalent input biasing current. The theoretical noise analysis of the proposed topology covers most of the noise sources of the circuit. Simulations show that the input-referred noise level of the circuit is 13.4nV/√Hz for a power consumption of 85µA with a power supply from 1.8V to 3.6V.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 397-404
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A 400 fJ per-cycle frequency reference for internet of things
Autorzy:
Coustans, M.
Krummenacher, F.
Terrier, C.
Kayal, M.
Powiązania:
https://bibliotekanauki.pl/articles/397716.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
time reference
supply voltage insensitivity
temperature insensitivity
ultra-low power
always on domain optimization
odniesienie czasowe
napięcie zasilające
ultra low power
Opis:
This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted timekeeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultralow power operation in 0.18 μm CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [-40°C - 60°C] and 0.07 %/V supply sensitivity.
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 2; 41-46
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Wearable biosensing: signal processing and communication architectures issues
Autorzy:
Celka, P.
Vetter, R.
Renevey, P.
Verjus, C.
Neuman, V.
Luprano, J.
Decotignie, J. D.
Piguet, C.
Powiązania:
https://bibliotekanauki.pl/articles/309491.pdf
Data publikacji:
2005
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
wearable sensors
wireless BAN
biosignal processing
low-power DSP
Opis:
Long-term monitoring of human vital signs is becoming one of the most important fields of research of biomedical engineering. In order to achieve weeks to months of monitoring, new strategies for sensing, conditioning, processing and communication have to be developed. Several strategies are emerging and show different possible architectures. This paper essentially focuses on issues in wearable biosignal processing and communication architecture currently running at the Swiss Center for Electronics and Microtechnology (CSEM) in the framework of several European projects.
Źródło:
Journal of Telecommunications and Information Technology; 2005, 4; 90-104
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Weryfikacja czasów obliczeń heurystycznych algorytmów redukcji poboru mocy układów cyfrowych CMOS
Computational time verification of heuristic algorithms forlIow power design of CMOSs circuits
Autorzy:
Szcześniak, W.
Powiązania:
https://bibliotekanauki.pl/articles/268918.pdf
Data publikacji:
2008
Wydawca:
Politechnika Gdańska. Wydział Elektrotechniki i Automatyki
Tematy:
redukcja poboru mocy
cyfrowe układy CMOS
heurystyczne algorytmy redukcji poboru mocy
low power design
digital CMOS circuits
heuristic low power design algorithms
Opis:
W pracy zaprezentowano przeprowadzoną komputerową weryfikację czasów obliczeń piętnastu nowoutworzonych algorytmów heurystycznych dla potrzeb redukcji poboru mocy cyfrowych układów CMOS. W zrealizowanych badaniach eksperymentalnych wykorzystano ogólnodostępne przykłady testowe ISCAS, zaczerpnięte z laboratorium CBL. Uzyskane wyniki pozwalają na akceptację nowoopracowanych algorytmów redukcji poboru mocy układów CMOS z punktu widzenia ich złożoności obliczeniowej.
This paper presents a computer verification of computational complexity of 15 newly elaborated heuristic algorithmsfor low power design of digital CMOS circuits. The verified algorithms were tested against a set of commonly available ISCAS benchmarks from CBL laboratory. The computational complexities of the tested heuristic algorithms were verified experimentally.
Źródło:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej; 2008, 25; 151-154
1425-5766
2353-1290
Pojawia się w:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Arc to Glow Transition for Using DC Low Power Switches in Low Voltage Electric Grids
Autorzy:
Wisniewski, G.
Powiązania:
https://bibliotekanauki.pl/articles/1202499.pdf
Data publikacji:
2017
Wydawca:
Politechnika Wrocławska. Oficyna Wydawnicza Politechniki Wrocławskiej
Tematy:
switching arc DC
low voltage
low power installation
arc-to-glow transition
Opis:
This paper presents and discusses results of analysis and investigations of arc to glow transformation phenomenon at contact opening, under DC inductive loads of low power (≤10 J) and low voltage (≤250 V). The proportion in duration of arcing and glowing is investigated in dependence on current and voltage value, contact material properties. The transition phenomenon is analyzed by means of fast photography and emission spectroscopy to complete the study. On the basis of investigated results the conclusions about the possibility of control of the arc to glow transformation for practical use in DC low voltage and low power electrical grids are formulated.
Źródło:
Present Problems of Power System Control; 2017, 8; 31-40
2084-2201
Pojawia się w:
Present Problems of Power System Control
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low-Power High-Speed Double Gate 1-bit Full Adder Cell
Autorzy:
Kumar, R.
Roy, S.
Bhunia, C. T.
Powiązania:
https://bibliotekanauki.pl/articles/226653.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
low-power full-adder
low-power CMOS design
multiplexer based full-adder design
multi-threshold voltage based full-adder design
pass transmission logic
Opis:
In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 4; 329-334
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of broadband power line communication module for automatic meter reading
Autorzy:
Chen, Xia
Liu, Ling
Powiązania:
https://bibliotekanauki.pl/articles/949869.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
automatic meter reading
low-power consumption
long-distance transmission
power line communication
Opis:
Low-power consumption and long-distance transmission are two problems that have to be solved by the application of broadband power line communication for the automatic meter reading system. To reduce the power consumption of the communication module, based on the analysis of the composition of the power consumption, some methods are proposed. From the communication chip level and the module circuit level, the design scheme of low-power consumption is given. To solve the problem of transmission distance, a frequency band of 2.44 MHz~5.6 MHz is used as the main working frequency band. The communication module supports multiple frequency bands. Using this feature, the optimal frequency band is adaptively selected for communication and automatic switching, which further improve the transmission distance. Field application shows that the above methods effectively decrease the power consumption of the communication module and extend the transmission distance.
Źródło:
Archives of Electrical Engineering; 2020, 69, 4; 771-780
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology
Autorzy:
Abdollahi, Hassan
Hooshmand, Reza
Owlia, Hadi
Powiązania:
https://bibliotekanauki.pl/articles/226818.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
current mode logic (CML)
graphene
graphene FET
low-power design
Opis:
In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 381-388
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
CMOS implementation of an analogue median filter for image processing in real time
Autorzy:
Jendernalik, W.
Jakusz, J.
Blakiewicz, G.
Szczepański, S.
Powiązania:
https://bibliotekanauki.pl/articles/202129.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analogue CMOS circuits
early vision processing
median filter
low-power
Opis:
An analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2013, 61, 3; 725-730
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
Autorzy:
Smaani, Billel
Meraihi, Yacin
Nafa, Fares
Benlatreche, Mohamed Salah
Akroum, Hamza
Latreche, Saida
Powiązania:
https://bibliotekanauki.pl/articles/2055208.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
double-gate MOSFET
compact model
ultra low power analog circuits
Opis:
This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multiobjective Design of Wireless Ad Hoc Networks: Security, Real-Time and Lifetime
Autorzy:
Zdravko, K.
Powiązania:
https://bibliotekanauki.pl/articles/308972.pdf
Data publikacji:
2009
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
ad hoc networks
low-power routing
multihop communication
secure routing
Opis:
This paper deals with the tradeoffs between security, real-time and lifetime performance. Due to the multihop nature of communication wireless ad hoc networks are very vulnerable to attacks. Malicious nodes included in a routing path may misbehave and organize attacks such as black holes. Scaling the number of hops for a packet delivery we trade off energy efficiency against security and real-time communication. To study the multihop communication we propose a hierarchical communication model. The REWARD (receive, watch, redirect) algorithm for secure routing is employed as a main example for corrective actions. Symmetrical routing is a distinguish feature of protocols such as REWARD and we outline the threshold of conflict between power-efficient partitioning of communication links and symmetrical routing.
Źródło:
Journal of Telecommunications and Information Technology; 2009, 2; 13-21
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Selected hardware solutions used in the process of monitoring bioparameters
Autorzy:
Michnik, A.
Szczurek, Z.
Szuster, B.
Kubik, B.
Kowalski, P.
Powiązania:
https://bibliotekanauki.pl/articles/397967.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
body area networks
telemedicine
ultra-low power
inductive charging
ECG
GSR
Bluetooth Low Energy
BioSip
sieć sensorowa na powierzchni ciała
telemedycyna
ultra low power
ładowanie indukcyjne
EKG
Opis:
The paper presents the idea behind the implementation of a system designed to monitor biomedical parameters and the subject's behaviour on the basis of the architecture of measurement modules located on the body. The system was developed as a result of market launch of new generations of electronic devices combining high functionality, small size and low power consumption. The paper presents the elements of the system called BioSip, along with hardware solutions selected for the objectives to be accomplished, i.e. providing communication between system elements that would be efficient and resistant to artefacts, extending the time of operation for battery power supply, as well as ensuring a satisfactory level of reliability and ease of use.
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 1; 26-32
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Architektura niskoenergetycznego uniwersalnego sterownika programowalnego
Architecture of Low Energy Universal Programmable Controller
Autorzy:
Hubacz, Marcin
Pawłowicz, Bartosz
Trybus, Bartosz
Powiązania:
https://bibliotekanauki.pl/articles/2174230.pdf
Data publikacji:
2022
Wydawca:
Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
Tematy:
PLC
Internet Rzeczy
Low Power
IEC 61131-3
Internet of Things
Opis:
Artykuł przedstawia koncepcję budowy architektury niskoenergetycznego sterownika programowalnego opracowanego zgodnie z normą IEC 61131-3. Uniwersalność dotyczy swobody wyboru jednostki centralnej oraz możliwości łatwej wymiany algorytmu sterującego. Do proponowanego rozwiązania wybrana zostaje jedna z omówionych trzech metod opracowywania i dystrybucji oprogramowania. W ramach prac przygotowany został prototypowy sterownik w oparciu o elementy ewaluacyjne, z przeznaczeniem do pracy w środowisku rozproszonym. W artykule przedstawiono również porównanie wydajności energetycznej wybranych układów STM32 z kilku odmiennych serii.
The article presents the concept of building a low-energy programmable controller architecture developed in accordance with the IEC 61131-3 standard. The universality concerns the freedom of choice of the central unit and the possibility of easy replacement of the control algorithm. One of the three methods of software development and distribution is selected for the proposed solution. As part of the work, a prototype controller was prepared based on evaluation elements, intended to work in a distributed environment. The article also presents a comparison of the energy efficiency of selected STM32 systems from several different series.
Źródło:
Pomiary Automatyka Robotyka; 2022, 26, 4; 79--84
1427-9126
Pojawia się w:
Pomiary Automatyka Robotyka
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Minimalizacja poboru mocy wspólnego modelu automatów skończonych
Minimisation of power dissipation of FSM common model
Autorzy:
Salauyou, V.
Grześ, T.
Powiązania:
https://bibliotekanauki.pl/articles/154327.pdf
Data publikacji:
2009
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
automat skończony
minimalizacja poboru mocy
finite state machine
low power design
Opis:
W artykule przedstawiono nowy algorytm kodowania stanów wewnętrznych automatu skończonego o obniżonym poborze mocy. Zastosowano w nim wspólny model automatu klas ADE co pozwoliło to na zmniejszenie ilości przerzutników przechowujących kod stanu. Badania symulacyjne przeprowadzone z wykorzystaniem standardowych układów testowych potwierdziły skuteczność kodowania z wykorzystaniem proponowanego algorytmu w porównaniu z algorytmami JEDI oraz NOVA, jak i zawartymi we wcześniejszych pracach autorów.
In this paper there is addressed the problem of power minimisation of the finite state machine (FSM). Power reduction is of great importance in design of digital systems as it can improve the speed and extend the time between recharging the batteries in mobile systems. In the common model of the FSM of class ADE (Section 2) the set A of internal states consists of three subsets: AA, AD, and AE. AA is the set of internal states of the FSM of class A, AD is the set of internal states of the FSM of class D (the output vector is identical to the next state code), and AE is the set of internal states of the FSM of class E (the input vector is identical to the next state code) [12]. The common model of the FSM of class ADE requires an additional register used for storing the input and output vector values. These registers are present in modern programmable logic devices. In Section 3 there is proposed a new algorithm of the FSM state assignment that makes use of the common model. The assigned code consists of three parts: G - input vector, Z - output vector and E - state code. G and Z are stored in the input and output registers, respectively. With this algorithm it is possible to assign codes that are shorter than those assigned with use of classical methods, and thus less power is dissipated in registers storing the current state code during every transition. The experimental results (Section 4, Tables 1 and 2) show the significant reduction (of 13 to 51%) in power dissipation compared to classic (JEDI, NOVA, column-based) and recent (sequential and iterating) algorithms.
Źródło:
Pomiary Automatyka Kontrola; 2009, R. 55, nr 7, 7; 491-493
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Energy harvester based on Terfenol-D for low power devices
Autorzy:
Mech, R.
Kaleta, J.
Lewandowski, D.
Wiewiórski, P.
Powiązania:
https://bibliotekanauki.pl/articles/1190061.pdf
Data publikacji:
2014
Wydawca:
Politechnika Wrocławska. Oficyna Wydawnicza Politechniki Wrocławskiej
Tematy:
pozyskiwanie energii
mikrokontroler
materiał inteligentny
harvesting energy
low-power microcontroller
smart material
Opis:
Rising requirements for a new constructions, force engineers to monitor them all day long. An attractive solution seems to be applications of wireless sensors. However, there is a barrier limiting their application, which is the need to supply them with an electrical power over extended period of time without using additional wiring or batteries. The potential solution of this problem seems to be an energy harvesting. This paper proposes a new energy harvesting device based on magnetostrictive material. In the course of the experiments with using Terfenol-D rods as actuators and sensors it has been shown, that the mechanical impact to the magnetic core based on Terfenol-D rod, NdFeB permanent magnets and coil set allowed to obtain an electric power signal enough to supply device of 100 Ohm load on their active state.
Źródło:
Interdisciplinary Journal of Engineering Sciences; 2014, 2, 1; 8--12
2300-5874
Pojawia się w:
Interdisciplinary Journal of Engineering Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays
Autorzy:
Rydygier, P.
Dąbrowski, W.
Fiutowski, T.
Wiącek, P.
Powiązania:
https://bibliotekanauki.pl/articles/226679.pdf
Data publikacji:
2010
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analogue multiplexer
low power amplifier
multi-channel electronics
multielectrode arrays
neural signal
Opis:
In the paper we present the design and test resultsof an integrated circuit combining a sample & hold circuit andan analogue multiplexer. The circuit has been designed as abuilding block for a multi-channel Application Specific IntegratedCircuit (ASIC) for recording signals from alive neuronal tissueusing high-density micro-electrode arrays (MEAs). The designis optimised with respect to critical requirements for suchapplications, i.e. short sampling time, low power dissipation, goodl inearity and high dynamic range. Presented design comprisessample&hold circuits with class AB operational amplifier, novelshift register, which allows minimising cross-coupling of the clocksignal and control logic. The circuit has been designed in 0.35µm CMOS process and has been successfully implemented in aprototype multi-channel ASIC.
Źródło:
International Journal of Electronics and Telecommunications; 2010, 56, 4; 399-404
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
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