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    Wyświetlanie 1-6 z 6
    Tytuł:
    Comparison of gate leakage current components in metal-insulator-semiconductor structures with high-k gate dielectris
    Autorzy:
    Janik, T.
    Jakubowski, A.
    Majkusiak, B.
    Korwin-Pawłowski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/308423.pdf
    Data publikacji:
    2001
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    MIS structures
    ultrathin dielectrics
    high-k dielectrics
    Opis:
    Numerical simulations of the gate leakage current in metal-insulator-semiconductor (MIS) structures based on the transfer matrix approach were carried out. They show contribution of different components of this current in MIS structures with best known high-k dielectrics such as Ta2O5 and TiO2. The comparison of the gate leakage current in MIS structures with SiO2 layer as well Ta2O5 and TiO2 layers is presented as well. Additionally, the minimum Si electron affinity to a gate dielectric which allows to preserve given level of the gate leakage current is proposed.
    Źródło:
    Journal of Telecommunications and Information Technology; 2001, 1; 65-69
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Review and perspective of high-k dielectrics on silicon
    Autorzy:
    Hall, S.
    Buiu, O.
    Mitrovic, I. Z.
    Lu, Y.
    Davey, W. M.
    Powiązania:
    https://bibliotekanauki.pl/articles/309000.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    high-k dielectrics
    dielectric constant
    hafnia
    interfacial layer
    aluminates
    silicates
    Opis:
    The paper reviews recent work in the area of high-k dielectrics for application as the gate oxide in advanced MOSFETs. Following a review of relevant dielectric physics, we discuss challenges and issues relating to characterization of the dielectrics, which are compounded by electron trapping phenomena in the microsecond regime. Nearly all practical methods of preparation result in a thin interfacial layer generally of the form SiOx or a mixed oxide between Si and the high-k so that the extraction of the dielectric constant is complicated and values must be qualified by error analysis. The discussion is initially focussed on HfO2 but recognizing the propensity for crystallization of that material at modest temperatures, we discuss and review also, hafnia silicates and aluminates which have the potential for integration into a full CMOS process. The paper is concluded with a perspective on material contenders for the "end of road map" at the 22 nm node.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 2; 33-43
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Characterization of Al2O3/4H-SiC and Al2O3/SiO2/4H-SiC MOS structures
    Autorzy:
    Taube, A.
    Guziewicz, M.
    Kosiel, K.
    Gołaszewska-Malec, K.
    Król, K.
    Kruszka, R.
    Kamińska, E.
    Piotrowska, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/953063.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    aluminum oxide
    MOS
    silicon carbide
    4H-SiC
    high-K dielectrics
    tlenek glinu
    węglik krzemu
    dielektryki high-k
    Opis:
    The paper presents the results of characterization of MOS structures with aluminum oxide layer deposited by ALD method on silicon carbide substrates. The effect of the application of thin SiO2 buffer layer on the electrical properties of the MOS structures with Al2O3 layer has been examined. Critical electric field values at the level of 7.5–8 MV/cm were obtained. The use of 5 nm thick SiO2 buffer layer caused a decrease in the leakage current of the gate by more than two decade of magnitude. Evaluated density of trap states near the conduction band of silicon carbide in Al2O3/4H-SiC MOS is about of 1×1013 eV−1cm−2. In contrast, the density of the trap states in the Al2O3/SiO2/4H-SiC structure is lower about of one decade of magnitude i.e. 1×1012 eV−1cm−2. A remarkable change in the MOS structure is also a decrease of density of electron traps located deeply in the 4H-SiC conduction band below detection limit due to using of the SiO2 buffer layer.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 3; 537-551
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Gate dielectrics: process integration issues and electrical properties
    Autorzy:
    Schwalke, U.
    Powiązania:
    https://bibliotekanauki.pl/articles/308978.pdf
    Data publikacji:
    2005
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    high-k dielectrics
    CMOS
    Pr2O3
    process integration
    resist removal
    wet chemical cleaning
    wet chemical etching
    RIE
    Opis:
    In this work we report on the process integration of crystalline praseodymium oxide (Pr2O3) high-k gate dielectric. Key process steps that are compatible with the high-k material have been developed and were applied for realisation of MOS structures. For the first time Pr2O3 has been integrated successfully in a conventional MOS process with n+ poly-silicon gate electrode. The electrical properties of Pr2O3 MOS capacitors are presented and discussed.
    Źródło:
    Journal of Telecommunications and Information Technology; 2005, 1; 7-10
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Challenges for 10 nm MOSFET process integration
    Autorzy:
    Östling, M.
    Malm, B. G.
    Haartman, M.
    Hallstedt, J.
    Zhang, Z.
    Hellström, P. E.
    Zhang, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/309004.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    sstrained silicon
    silicon-germanium
    silicon-on-insulator (SOI)
    high-k dielectrics
    hafnium oxide
    nanowire
    low frequency noise
    mobility
    metal gate
    Opis:
    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 2; 25-32
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Charging Phenomena at the Interface Between High-k Dielectrics and SiOx Interlayers
    Autorzy:
    Engström, O.
    Raeissi, B.
    Piscator, J.
    Mitrovic, I. Z.
    Hall, S.
    Gottlob, H. D. B.
    Schmidt, M.
    Hurley, P. K.
    Cherkaoui, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/308138.pdf
    Data publikacji:
    2010
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    defects
    dielectrics
    high-k
    metal oxide semiconductor
    Opis:
    The transition regions of GdSiO/SiOx and HfO2/ SiOx interfaces have been studied with the high-k layers deposited on silicon substrates. The existence of transition regions was verified by medium energy ion scattering (MEIS) data and transmission electron microscopy (TEM). From measurements of thermally stimulated current (TSC), electron states were found in the transition region of the HfO2/SiOx structures, exhibiting instability attributed to the flexible structural molecular network expected to surround the trap volumes. The investigations were focused especially on whether the trap states belong to an agglomeration consisting of a single charge polarity or of a dipole constellation. We found that flat-band voltage shifts of MOS structures, that reach constant values for increasing oxide thickness, cannot be taken as unique evidence for the existence of dipole layers.
    Źródło:
    Journal of Telecommunications and Information Technology; 2010, 1; 10-19
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-6 z 6

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