Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

Wyszukujesz frazę "field-programmable gate array" wg kryterium: Temat


Tytuł:
An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine
Autorzy:
Mahendra, H. N.
Mallikarjunaswamy, S.
Powiązania:
https://bibliotekanauki.pl/articles/2134051.pdf
Data publikacji:
2022
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
support vector machine
SVM
central processing unit
CPU
digital signal processor
DSP
field programmable gate array
FPGA
high level synthesis
HLS
hardware description language
HDL
Opis:
This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.
Źródło:
International Journal of Electronics and Telecommunications; 2022, 68, 3; 609--617
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Employing FPGA DSP blocks for time-to-digital conversion
Autorzy:
Kwiatkowski, Paweł
Powiązania:
https://bibliotekanauki.pl/articles/221505.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
time-to-digital converter
time coding line
time interval counter
digital signal processing
field-programmable gate array
Opis:
The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.
Źródło:
Metrology and Measurement Systems; 2019, 26, 4; 631-643
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A time-domain pulse amplitude and width discrimination method for photon counting
Autorzy:
del Mar Correa, M.
Pérez, F. R.
Powiązania:
https://bibliotekanauki.pl/articles/220971.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
field-programmable gate array
time-to-digital converter
spectroscopy
photomultiplier
photon counting
discriminator
after-pulsing
low-voltage differential signalling
Opis:
This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a multiphase TDC using delay lines shorter than a single clock period is also described. The performance of this signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.
Źródło:
Metrology and Measurement Systems; 2018, 25, 2; 269-282
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A High-Speed Fully Digital Phase-Synchronizer Implemented in a Field Programmable Gate Array Device
Autorzy:
Frankowski, R.
Chaberski, D.
Kowalski, M.
Zieliński, M.
Powiązania:
https://bibliotekanauki.pl/articles/221125.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
phase synchronizer
delay line
coincidence counting
quantum information
time interval measurement
time-to-digital converters
field programmable gate array (FPGA)
Opis:
Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.
Źródło:
Metrology and Measurement Systems; 2017, 24, 3; 537-550
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An efficient hardware implementation of a combinations generator
Autorzy:
Mazurkiewicz, T.
Powiązania:
https://bibliotekanauki.pl/articles/298447.pdf
Data publikacji:
2017
Wydawca:
Uniwersytet Warmińsko-Mazurski w Olsztynie
Tematy:
information technology
generator of combinations
field programmable gate array (FPGA)
Opis:
In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.
Źródło:
Technical Sciences / University of Warmia and Mazury in Olsztyn; 2017, 20(4); 405-413
1505-4675
2083-4527
Pojawia się w:
Technical Sciences / University of Warmia and Mazury in Olsztyn
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FPGA implementation of logarithmic versions of Baum-Welch and Viterbi algorithms for reduced precision hidden Markov models
Autorzy:
Pietras, M.
Klęsk, P.
Powiązania:
https://bibliotekanauki.pl/articles/201874.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
hidden Markov models
numerical stability
Viterbi algorithm
parallel architecture
field-programmable gate array
ukryte modele Markowa
stabilność numeryczna
Algorytm Viterbiego
architektura równoległa
Opis:
This paper presents a programmable system-on-chip implementation to be used for acceleration of computations within hidden Markov models. The high level synthesis (HLS) and “divide-and-conquer” approaches are presented for parallelization of Baum-Welch and Viterbi algorithms. To avoid arithmetic underflows, all computations are performed within the logarithmic space. Additionally, in order to carry out computations efficiently – i.e. directly in an FPGA system or a processor cache – we postulate to reduce the floating-point representations of HMMs. We state and prove a lemma about the length of numerically unsafe sequences for such reduced precision models. Finally, special attention is devoted to the design of a multiple logarithm and exponent approximation unit (MLEAU). Using associative mapping, this unit allows for simultaneous conversions of multiple values and thereby compensates for computational efforts of logarithmic-space operations. Design evaluation reveals absolute stall delay occurring by multiple hardware conversions to logarithms and to exponents, and furthermore the experiments evaluation reveals HMMs computation boundaries related to their probabilities and floating-point representation. The performance differences at each stage of computation are summarized in performance comparison between hardware acceleration using MLEAU and typical software implementation on an ARM or Intel processor.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2017, 65, 6; 935-946
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System
Klasyfikacja rodzaju defektów tkanin za pomocą probabilistycznej sztucznej sieci neuronowej oraz za pomocą systemu FPGA
Autorzy:
Hasnat, A.
Ghosh, A.
Khatun, A.
Halder, S.
Powiązania:
https://bibliotekanauki.pl/articles/234369.pdf
Data publikacji:
2017
Wydawca:
Sieć Badawcza Łukasiewicz - Instytut Biopolimerów i Włókien Chemicznych
Tematy:
classification
fabric defect
field programmable gate array (FPGA)
radial basis function
probabilistic neural network
klasyfikacja wad tkanin
probabilistyczna sieć neuronowa
Opis:
This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.
W pracy zaprezentowano system klasyfikacji wad tkanin przy użyciu probabilistycznej sieci neuronowej (PNN) i przy zastosowaniu systemu Field Programmable Gate Array (FPGA). PNN pozwala na osiągnięcie dokładności 98 ± 2% dla zbioru danych testowych, podczas gdy system FPGA pozwala na osiągnięcie dokładności około 94 ± 2%. System FPGA pracuje przy częstotliwości 50,777 MHz, co odpowiada 19,694 ns.
Źródło:
Fibres & Textiles in Eastern Europe; 2017, 1 (121); 42-48
1230-3666
2300-7354
Pojawia się w:
Fibres & Textiles in Eastern Europe
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A proposal of output speed multiplication technique for true random number generators based on ring oscillators
Autorzy:
Matuszewski, Ł.
Kubczak, P.
Powiązania:
https://bibliotekanauki.pl/articles/114218.pdf
Data publikacji:
2016
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
restart mechanism
Opis:
Nowadays modern cryptographic systems require a tremendous amount of keys. Very fast random number generators (RNGs) are needed to produce those keys in the requested time, but what to do when a solution that is already in use reaches the maximum speed? The aim of the paper is to find the answer to this question. In addition, generated random numbers should not leave a cryptographic system, because according to the Kerckhoffs thesis, the security of the whole system should be based only on a key. The cryptographic system should be enclosed within a single chip. In order to check new ideas and prove them, there were used NIST 800-22 test suite and restarts mechanism. The basic concept of the generator built of ring oscillators is still the same; ring oscillators are combined by XOR gates tree. A single ring oscillator consists of inverter, latch and NAND. This kind of construction provides a tool to make synchronous start and stop of all oscillators and the restart mechanism technique is applied in this manner. The speed of generation was increased by using multiple parallel generator trees to generate instantly the whole n-bit word. The paper shows that reproduction of the base structure is not a simple method of increasing the speed of generator. Moreover, it is always important to carefully consider all new ideas, because even if the NIST statistical test suite is passed, there is a chance that the restart mechanism will show some correlations that can be used during attack on the system.
Źródło:
Measurement Automation Monitoring; 2016, 62, 5; 157-159
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Research and Medical Transcranial Doppler System
Autorzy:
Lewandowski, M.
Walczak, M.
Karwat, P.
Witek, B.
Karłowicz, P.
Powiązania:
https://bibliotekanauki.pl/articles/177389.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
Doppler system
digital signal processing
hardware-software partitioning
field programmable gate array (FPGA)
Opis:
A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a numer of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.
Źródło:
Archives of Acoustics; 2016, 41, 4; 773-781
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing
Autorzy:
Łoza, S.
Matuszewski, Ł.
Jessa, M.
Powiązania:
https://bibliotekanauki.pl/articles/963943.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
random numbers
cryptography
ring oscillators
hash functions
field programmable gate array (FPGA)
Opis:
Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.
Źródło:
International Journal of Electronics and Telecommunications; 2015, 61, 2; 199-204
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A random number generator using ring oscillators and the Keccak as post-processing
Autorzy:
Łoza, S.
Matuszewski, Ł.
Jessa, M.
Kubczak, P.
Powiązania:
https://bibliotekanauki.pl/articles/114620.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
hash function
Opis:
In cryptography, sequences of numbers with unpredictable elements are often required. Such sequences should pass all known statistical tests for random sequences. Because sequences produced in real circuits are biased, they do not pass many statistical tests, e.g., the distribution of numbers is not uniform. Such random number sequences should be subjected to a transformation called post-processing. In this paper, a true random number generator is considered. It uses ring oscillators and the Keccak hash function as post-processing. This paper presents only simulation conditions for this approach since the post-processing part was done using x86 architecture on a PC.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 290-292
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Digital random bit generators implemented in FPGAs offered by various manufacturers
Autorzy:
Kubczak, P.
Matuszewski, Ł.
Jessa, M.
Łoza, S.
Powiązania:
https://bibliotekanauki.pl/articles/114475.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
Opis:
In cryptography, we require that a random sequence should have excellent statistical properties as well as non-deterministic character. Combining multiple independent sources of randomness using the modulo two operation, significantly improves the statistical properties of the generated sequences and also affects the accumulation of true randomness generated in the oscillator sources. This is a very promising method of producing random sequences. In this paper, we compare the implementations of the RO-based combined random generator in various FPGAs technologies offered by various manufactures (Xilinx, Altera, Lattice). In this research, we used a NIST 800-22 statistical test suite to assess the statistical properties. The results show that the method of producing strings with a combined generator is the method stable in terms of technology. The results are similar for implementation in all FPGA used in the experiment. So, the proposed generator can be implemented in various programmable structures together with other components of a cryptographic system.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 293-295
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pulse Sequence Shaper For Radiospectroscopy And Relaxation Methods In NQR
Autorzy:
Bobalo, Y.
Hotra, Z.
Hotra, O.
Politans’kyy, L.
Samila, A.
Powiązania:
https://bibliotekanauki.pl/articles/221794.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
NQR
pulse sequence
field programmable gate array (FPGA)
frequency synthesizer
Opis:
A pulse sequence shaper for the pursuance of the research using a wide spectrum of radiospectroscopy and relaxation methods in NQR is proposed. The distinctive feature of this product is its implementation with the application of a multi-functional programmable frequency synthesizer suitable for high-speed amplitude and phase manipulations.
Źródło:
Metrology and Measurement Systems; 2015, 22, 3; 363-370
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Development of an embedded FPGA-based data acquisition system dedicated to zero power reactor noise experiments
Autorzy:
Arkani, M.
Khalafi, H.
Vosoughi, N.
Powiązania:
https://bibliotekanauki.pl/articles/220709.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
zero power reactor (ZPR) noise
time interval measurement
probability distribution function (PDF)
field programmable gate array (FPGA)
data acquisition system (DAS)
nuclear reactor
neutron detection
Opis:
An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.
Źródło:
Metrology and Measurement Systems; 2014, 21, 3; 433-446
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FPGA realization of an improved alpha max plus beta min algorithm
Autorzy:
Czyżak, M.
Smyk, R.
Powiązania:
https://bibliotekanauki.pl/articles/376709.pdf
Data publikacji:
2014
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
square root computation
alpha max plus beta min algorithm
field programmable gate array (FPGA)
Opis:
The improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. The improved version allows to reduce the peak error from about 4% to 0.33%. This is attained by determination of the approximate ratio of arguments and adequate selection of algorithm coefficients. Four approximation regions are used and hence four sets of coefficients. Also a Xilinx FPGA implementation for 12-bit sign magnitude numbers is shown.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 151-160
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł

Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies