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    Wyświetlanie 1-5 z 5
    Tytuł:
    Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
    Autorzy:
    Smaani, Billel
    Meraihi, Yacin
    Nafa, Fares
    Benlatreche, Mohamed Salah
    Akroum, Hamza
    Latreche, Saida
    Powiązania:
    https://bibliotekanauki.pl/articles/2055208.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    double-gate MOSFET
    compact model
    ultra low power analog circuits
    Opis:
    This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET
    Autorzy:
    Dargar, Abha
    Srivastava, Viranjay M.
    Powiązania:
    https://bibliotekanauki.pl/articles/1844602.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    short-channel effects
    metal oxide semiconductor
    transistor
    cylindrical surrounding double-gate
    dual-material gate
    microelectronics
    nanotechnology
    Opis:
    In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 1; 29-34
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Area equivalent WKB Compact modeling approach for tunneling probability in Hetero-Junction TFETs including ambipolar behaviour
    Autorzy:
    Horst, Fabian
    Farokhnejad, Atieh
    Darbandy, Ghader
    Iñíguez, Benjamín
    Kloes, Alexander
    Powiązania:
    https://bibliotekanauki.pl/articles/397787.pdf
    Data publikacji:
    2018
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    TFET
    tunneling probability
    WKB approximation
    heterojunction
    compact modeling
    closed-form
    double-gate
    DG
    ambipolarity
    modelowanie kompaktowe
    dwubiegunowość
    Opis:
    This paper introduces an innovative modeling approach for calculating the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs). The field of application is the usage in TFET compact models. Looking at a tunneling process in TFETs, carriers try to tunnel through an energy barrier which is defined by the device band diagram. The tunneling energy barrier is approximated by an approach which assumes an area equivalent (AE) triangular shaped energy profile. The simplified energy triangle is suitable to be used in the Wentzel-Kramers-Brillouin (WKB) approximation. Referring to the area instead of the electric field at individual points is shown to be a more robust approach in terms of numerical stability. The derived AE approach is implemented in an existing compact model for double-gate (DG) TFETs. In order to verify and show the numerical stability of this approach, modeling results are compared to TCAD Sentaurus simulation data for various sets of device parameters, whereby the simulations include both ON- and AMBIPOLAR-state of the TFET. In addition to the various device dimensions, the source material is also changed to demonstrate the feasibility of simulating hetero-junctions. Comparing the modeling approach with TCAD data shows a good match. Apart the limitations demonstrated and discussed in this paper, the main advantage of the AE approach is the simplicity and a better fit to TCAD data in comparison to the quasi-2D WKB approach.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2018, 9, 2; 47-59
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Rapid NEGF-based calculation of ballistic current in ultra-short DG MOSFETs for circuit simulation
    Autorzy:
    Hosenfeld, F.
    Horst, F..
    Graef, M.
    Farokhnejad, A.
    Kloes, A.
    Iniguez, B.
    Lime, F.
    Powiązania:
    https://bibliotekanauki.pl/articles/397995.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    ultra-short Double-Gate MOSFET
    nonequilibrium Green's function
    NEGF
    ballistic transport
    source-to-drain tunneling
    ultra-thin body
    UTB
    compact model
    multi-scale simulation
    nierównowagowe funkcje Greena
    transport balistyczny
    tunelowanie źródło-dren
    model kompaktowy
    symulacja wieloskalowa
    Opis:
    Shrinking gate length in conventional MOSFETs leads to increasing short channel effects like source-to-drain (SD) tunneling. Compact modeling designers are challenged to model these quantum mechanical effects. The complexity lies in the set-up between time efficiency, physical model relation and analytical equations. Multi-scale simulation bridges the gap between compact models, its fast and efficient calculation of the device terminal voltages, and numerical device models which consider the effects of nanoscale devices. These numerical models iterate between Poisson- and Schroedinger equation which significantly slows down the simulation performance. The physicsbased consideration of quantum effects like the SD tunneling makes the non-equilibrium Green’s function (NEGF) to a stateof-the-art method for the simulation of devices in the sub 10 nm region. This work introduces a semi-analytical NEGF model for ultra-short DG MOSFETs. Applying the closed-form potential solution of a classical compact model, the model turns the NEGF from an iterative numerical solution into a straightforward calculation. The applied mathematical approximations speed up the calculation time of the 1D NEGF. The model results for the ballistic channel current in DG-MOSFETs are compared with numerical NanoMOS TCAD [1] simulation data. Shown is the accurate potential calculation as well as the good agreement of the current characteristic for temperatures down to 75 K for channel lengths from 6 nm to 20 nm and channel thickness from 1.5 nm to 3 nm.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 2; 65-72
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Simulation framework and thorough analysis of the impact of barrier lowering on the current in SB-MOSFETs
    Autorzy:
    Schwarz, M.
    Calvet, L. E.
    Snyde, J. P.
    Krauss, T.
    Schwalke, U.
    Kloes, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/397793.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    2D Poisson equation
    device modeling
    double-gate MOSFET
    field emission
    framework
    Schottky barrier
    Synopsys
    TCAD
    thermionic emission
    thermionic current
    tunneling current
    dwuwymiarowe równanie Poissona
    modelowanie elementów elektronicznych
    dwubramkowy tranzystor MOS
    emisja polowa
    bariera Schottky'ego
    emisja termoelektronowa
    prąd termoelektronowy
    prąd tunelowy
    Opis:
    In this paper we present a simulation framework to account for the Schottky barrier lowering models in SBMOSFETs within the Synopsys TCAD Sentaurus tool-chain. The improved Schottky barrier lowering model for field emission is considered. A strategy to extract the different current components and thus accurately predict the on- and off-current regions are adressed. Detailed investigations of these components are presented along with an improved Schottky barrier lowering model for field emission. Finally, a comparison for the transfer characteristics is shown for simulation and experimental data.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2017, 8, 2; 72-79
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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