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Wyświetlanie 1-15 z 86
Tytuł:
Compact terahertz devices based on silicon in CMOS and BiCMOS technologies
Autorzy:
But, Dmytro B.
Chernyadiev, Alexander V.
Ikamas, Kęstutis
Kołaciński, Cezary
Krysl, Anastasiya
Roskos, Hartmut G.
Knap, Wojciech
Lisauskas, Alvydas
Powiązania:
https://bibliotekanauki.pl/articles/2204176.pdf
Data publikacji:
2023
Wydawca:
Polska Akademia Nauk. Stowarzyszenie Elektryków Polskich
Tematy:
terahertz
teraFET
CMOS
THz emitter
THz detectors
Opis:
This paper reports on compact CMOS-based electronic sources and detectors developed for the terahertz frequency range. It was demonstrated that with the achievable noise-equivalent power levels in a few tens of pW/√Hz and the emitted power in the range of 100 μW, one can build effective quasi-optical emitter-detector pairs operating in the 200–266 GHz range with the input power-related signal-to-noise ratio reaching 70 dB for 1 Hz-equivalent noise bandwidth. The applicability of these compact devices for a variety of applications including imaging, spectroscopy or wireless communication links was also demonstrated.
Źródło:
Opto-Electronics Review; 2023, 31, 2; art. no. e144599
1230-3402
Pojawia się w:
Opto-Electronics Review
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and analysis of MOS based Magnetic Field Sensor
Autorzy:
Kumar, Rakesh
Powiązania:
https://bibliotekanauki.pl/articles/1075557.pdf
Data publikacji:
2019
Wydawca:
Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Tematy:
CMOS Technology
Hall Effect
Lorentz force
MagFET device
Magnetic sensor
Opis:
Magnetic sensors are widely used in various applications such as consumer electronic products (mobile phones, laptops), biomedical applications (brain function mapping), navigation, vehicle detection, mineral prospecting, non-contact switching (keyboard), contactless temperature measurement, wireless sensor network etc. Sensitivity of MagFET devices towards magnetic field, depends on the shape, dimensions VGS, VDS. In this paper we have measured effect of Physical design of gate on sensitivity of MagFET.
Źródło:
World Scientific News; 2019, 121; 42-47
2392-2192
Pojawia się w:
World Scientific News
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Capacitance/Resistance Modeling and Analog Performance Evaluation of 3-D SOI FinFET Structure for Circuit Perspective Applications
Autorzy:
Jain, Neeraj
Raj, Balwinder
Powiązania:
https://bibliotekanauki.pl/articles/1159723.pdf
Data publikacji:
2018
Wydawca:
Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Tematy:
CMOS
Integrated Circuits
Parasitic Capacitance
Parasitic Resistance
SOI FinFET
Opis:
This paper explores the capacitance and resistance modeling of 3-D (dimensional) SOI FinFET structure and circuit implementation approach is done for the utility of SOI FinFET structure. The scaling of the FinFET structure is continuously ongoing and increased parasitic and resistance affects the circuit level performance of SOI FinFET in ICs (Integrated Circuits) below 20 nm technology node. A geometrical-based analysis is done to get the optimized parasitic capacitance and resistance model and validity of the model is verified by three-dimensional (3-D) field solver Synopsys Raphael software. For utility of the developed model, some circuit implementation is done in h-spice simulation environment.
Źródło:
World Scientific News; 2018, 113; 194-209
2392-2192
Pojawia się w:
World Scientific News
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
CMOS ECCCII with Linear Tune of Rx and Its Application to Current-Mode Multiplier
Autorzy:
Sakul, C.
Powiązania:
https://bibliotekanauki.pl/articles/226547.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
electronically tunable
CCCII
current mode
CMOS
linear
Opis:
In this paper, the second-generation CMOS currentcontrolled-current-conveyor based on differential pair of operational transconductance amplifier has been researched and presented. Since the major improvement of its parasitic resistance at x-port can be linearly controlled by an input bias current, the proposed building block is then called “The Second-Generation Electronically-tunable Current-controlled Current Conveyor” (ECCCI). The applications are demonstrated in form of both 2 quadrant and 4 quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program from which the results are proved to be in agreement with the theory.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 385-390
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Improvements of high-voltage trapezoidal waveform edge-rounding circuit
Autorzy:
Jankowski, Mariusz
Powiązania:
https://bibliotekanauki.pl/articles/397803.pdf
Data publikacji:
2018
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
CMOS integrated circuits
high-voltage techniques
wireless communications
current-mode circuits
RFID tag
harmonic distortion
electromagnetic compatibility
układy scalone CMOS
techniki wysokonapięciowe
komunikacja bezprzewodowa
obwód prądowy
zniekształcenie harmoniczne
kompatybilność elektromagnetyczna
Opis:
This paper introduces a solution to a design problem caused by necessity of electromagnetic noise reduction in simple close-range wireless command and control systems, including Radio-frequency identification (RFID) systems. Trade-off between simplicity of data transmission, detection and decoding on one side vs. presence of high frequency harmonics in transmitted signals on the other makes some designers choose approach in which trapezoidal waveforms are used instead of rectangular ones. Moreover, edges of trapezoidal waveforms are additionally rounded to further limit presence of higher harmonics and thus to comply to EMI regulations and requirements. The paper proposes a solution based on a reimplementation of a high-voltage structure already proposed by the author, but implemented with use of different semiconductor technology process. Utilization of this new process and devices available in this technology makes possible significant increase of the circuit operation quality.
Źródło:
International Journal of Microelectronics and Computer Science; 2018, 9, 3; 93-100
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Matryce światłoczułe – właściwości, parametry, zastosowania
Photosensitive matrices – properties, parameters, applications
Autorzy:
Parzych, J.
Hulewicz, A.
Krawiecki, Z.
Powiązania:
https://bibliotekanauki.pl/articles/377387.pdf
Data publikacji:
2017
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
przetwornik CCD
przetwornik CMOS
Opis:
W niniejszym artykule omówiono zagadnienia związane z matrycami światłoczułymi stosowanymi w cyfrowej akwizycji oraz analizie obrazów: CCD i CMOS. Przedstawiono budowę, zasadę działania, rodzaje oraz parametry i właściwości obu typów matryc. Następnie przeanalizowano różnice oraz podobieństwa matryc CCD i CMOS wynikające m.in. z ich struktury i rodzaju. Ponadto omówiono obszary aplikacyjne matryc światłoczułych, zwracając jednocześnie uwagę na wpływ danego zastosowania i wymaganych parametrów na wybór: CMOS czy CCD.
In the present article they discussed issues concerning photosensitive matrices applied in the digital aquisition and analysis of images: CCD and CMOS. a structure, a principle of operation, types, parameters and properties of both types of matrices were described. Next differences and resemblances of CCD and CMOS matrices resulting among others from their structure and the kind were analysed. Moreover appliqué areas of were discussed, simultaneously considering the influence of the given application and required parameters on choice: CMOS or CCD.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2017, 92; 189-203
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Phaseone 190 MP aerial system: camera design principles and productivity analysis
Lotniczy system 190 MP: konstrukcja kamery i analiza jej wydajności
Autorzy:
Raizman, Y.
Powiązania:
https://bibliotekanauki.pl/articles/130054.pdf
Data publikacji:
2017
Wydawca:
Stowarzyszenie Geodetów Polskich
Tematy:
kamera średnioformatowa
wydajność
Phase One
CMOS
iXU-RS190
medium format camera
productivity
Opis:
Phase One next generation iXU-RS1900 aerial system is based on 100MP medium format camera. It comprises two 90 mm lenses and two CMOS image sensors with pixel size of 4.6 μm shifted outward according to the optical axis of the lenses. Each lens is vertically oriented, providing nadir images with an equal ground resolution. The two stitched images form a large frame with 16,470 pixels across the flight line and 11,570 pixels along the flight providing 190 MP image. The total FOV across flight line is 45.7 deg and FOV along flight line is 33 deg. Productivity analysis for aerial survey cameras may be expressed as an aerial survey productivity (image coverage per hour of flight), distance between flight lines, time required to fly AOI (Area of Interest), or number of flight lines per AOI. The new iXU-RS1900 camera enables an increase in the distance between flight lines and improves aerial survey productivity by 43%. It needs only 34 min of flight to cover the central area of most cities in Europe. Thus, with the new CMOS sensor and short exposure time, high quality aerial imagery may be reached without using an FMC technique.
Kamera lotnicza nowej generacji firmy Phase One iXU-RS190 bazuje na kamerze średnioformatowej 100MP. Łączy dwa obiektywy 90 mm i dwa przetworniki obrazu CMOS z pikselem 4.6 m, przesunięte na zewnątrz względem osi obiektywów. Każdy obiektyw ma pionowo zorientowaną oś, co daje jednakową rozdzielczość terenową zdjęć. Dwa połączone obrazy tworzą kadr o 16 470 pikselach w poprzek i 11 570 pikselach wzdłuż lotu, łącznie o rozdzielczości 190 Mpix. Odpowiada to kątom widzenia 45.7 i 33 odpowiednio w poprzek i wzdłuż lotu. Analiza wydajności kamer lotniczych może być wyrażana jako wydajność obrazowania (powierzchnia kryta zdjęcia na godzinę lotu), odległość między szeregami, czas lotu konieczny na pokrycie obszaru zainteresowania, czy liczbą szeregów na takim obszarze. Nowa kamera iXU-RS190 umożliwia zwiększenie odległości między szeregami i poprawia wydajność o 43%. Potrzebuje tylko 34 minuty lotu na pokrycie centralnej części większości miast europejskich. Z nowym przetwornikiem CMOS i krótkimi ekspozycjami wysoka jakość zdjęć lotniczych może być osiągnięta bez konieczności stosowania technik kompensacji rozmazania (FMC).
Źródło:
Archiwum Fotogrametrii, Kartografii i Teledetekcji; 2017, 29; 137-146
2083-2214
2391-9477
Pojawia się w:
Archiwum Fotogrametrii, Kartografii i Teledetekcji
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Upgraded low voltage analog Current-to-Voltage converter with negative feedback
Autorzy:
Wojtyna, R.
Powiązania:
https://bibliotekanauki.pl/articles/397781.pdf
Data publikacji:
2017
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
analog signal processing
current-to-voltage converters
feedback theory
analog CMOS electronics
analogowe przetwarzanie sygnałów
przetworniki prądowo-napięciowe
teoria sprzężenia zwrotnego
CMOS
Opis:
In this paper, an improved version of a current to voltage (C-V) converter is proposed. As compared to the previous version, the number of used transistors has been reduced by 1 and equals 7. The main results of this change are: an improvement of the circuit transfer function linearity, reduction the converter input resistance and decrease of the required supply voltage. Improvements in the considered converter results not only from the reduction of the number of the used transistors but also from the proposed realization of the feedback loop. In this way, it was possibly to get a strong loop gain. As a results, the achieved minimum supply voltage has been reduces from 2V, in case of the previous published converter version, to as low level as 1.2 V, in the case of the newly proposed solution. As for the linearity of the C-V transfer function, apart from its strong loop gain, an important role play also output transistors operating in a small drain to source region (linear region). Working in this region, one obtains a quasi linear voltage to current relationship. The theoretical and simulation results are in a good agreement and are promising.
Źródło:
International Journal of Microelectronics and Computer Science; 2017, 8, 2; 80-84
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A High-Efficient Low-Voltage Rectifier for CMOS Technology
Autorzy:
Jendernalik, W.
Jakusz, J.
Blakiewicz, G.
Kłosowski, M.
Powiązania:
https://bibliotekanauki.pl/articles/220356.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS rectifier
high frequency rectifier
wireless power transmission
Opis:
A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages.
Źródło:
Metrology and Measurement Systems; 2016, 23, 2; 261-268
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Automatic tuning of a resonant circuit in wireless power supply systems for biomedical sensors
Autorzy:
Blakiewicz, G.
Jakusz, J.
Jendernalik, W.
Szczepański, S.
Powiązania:
https://bibliotekanauki.pl/articles/201440.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS circuits
automatic tuning
impedance matching
resonant circuit
układy CMOS
tuning
impedancja
obwód rezonansowy
Opis:
In this paper, a tuning method of a resonant circuit suited for wireless powering of miniature endoscopic capsules is presented and discussed. The method allows for an automatic tuning of the resonant frequency and matching impedance of a full wave rectifier loading the resonant circuit. Thereby, the receiver tunes so as to obtain the highest power efficiency under given conditions of transmission. A prototype receiver for wireless power reception, fabricated in in AMS CMOS 0.35 μm technology, was used to verify correct operation of the proposed tuning. The prototype system produces a stable supply voltage, adjustable in the range of 1.2–1.8 V at a maximum output current of 100–67 mA, which is sufficient to power a typical endoscopic capsule.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 3; 641-646
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Comparative study on transistor based full adder designs
Autorzy:
Anitha, R.
Powiązania:
https://bibliotekanauki.pl/articles/1182905.pdf
Data publikacji:
2016
Wydawca:
Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Tematy:
Full Adder; CPL; DPL; CMOS; Transmission gates; Arithmetic Unit
Opis:
Recently in the generic systems the load on the processor is much heavy. The ability and the challenging process have ended with larger core operations are in the core processor. This paper is basically given special importance on different methodologies having been proposed for Adder, which is the basic operation of the Arithmetic unit. The wide research on the digital adders has been covered so many applications like designs of ALU, RISC, CISC processors, DSP used for data path arithmetic, low power CMOS, optical computing, Nanotechnology and so on. This paper gives greater knowledge and understanding about the various techniques that have amply used of Adder from the earlier years. In this paper we analyzed the implementation of different types of full Adders implemented using CMOS logic (Static CMOS and Dynamic CMOS), CMOS Transmission Gates, Pass Transistor Gates (CPL and DPL).
Źródło:
World Scientific News; 2016, 53, 3; 404-416
2392-2192
Pojawia się w:
World Scientific News
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low-Power High-Speed Double Gate 1-bit Full Adder Cell
Autorzy:
Kumar, R.
Roy, S.
Bhunia, C. T.
Powiązania:
https://bibliotekanauki.pl/articles/226653.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
low-power full-adder
low-power CMOS design
multiplexer based full-adder design
multi-threshold voltage based full-adder design
pass transmission logic
Opis:
In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 4; 329-334
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multiple output CMOS current amplifier
Autorzy:
Pankiewicz, B.
Powiązania:
https://bibliotekanauki.pl/articles/201141.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
current amplifier
current follower
current mirror
CMOS technology
wzmacniacz prądowy
prąd
technologia CMOS
Opis:
In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 301-306
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
On analog comparators for CMOS digital pixel applications. A comparative study
Autorzy:
Jendernalik, W.
Powiązania:
https://bibliotekanauki.pl/articles/200565.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS image sensor
CMOS digital pixel
analog comparator
fixed-pattern noise
FPN
CMOS
matryca świałoczuła CMOS
piksel cyfrowy
komparator analogowy
hałas ustalony
Opis:
Voltage comparator is the only - apart from the light-to-voltage converter - analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based on a very simple non-differential comparator with a reduced size and degraded performance. Theoretical analysis of the comparator nonideality effect on the quality of the image obtained from the digital pixel matrix as well as simulation results are provided.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 271-278
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 86

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