Autor: Sheela, T. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Evaluation of bio control efficacy of synbiotic cherry ( Prunus avium. L.,) juice
Autorzy:: Sheela, T.
Sathees Kannan, T.M.
Jayakumar, K.
Powiązania:: https://bibliotekanauki.pl/articles/10990.pdf
Data publikacji:: 2015
Wydawca:: Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Opis:: The aim of the research was to evaluate that the effect of symbiotic fermented cherry juice containing fructo oligosaccharide to enhance the growth and activity of probiotic strains include Lactobacillus acidophilus was tested for their antibiotic susceptibility, and tolerance to bile. Antifungal activity of symbiotic cherry juice could differ in their antagonistic activity against fungal disease which could be due to the metabolite secreted by the lactic acid bacteriocin specially type of organic acids and added fructo oligo saccharide as a probiotic and for food preservation synbiotic cherry juice was identified and their major compounds was detected using gas chromatographymass spectrum (gc-ms).
Źródło:: International Letters of Natural Sciences; 2015, 42
2300-9675
Pojawia się w:: International Letters of Natural Sciences
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks
Autorzy:: Velrajkumar, P.
Senthilpari, C.
Francisca, J. Sheela
Raj, T. Nirmal
Powiązania:: https://bibliotekanauki.pl/articles/226056.pdf
Data publikacji:: 2019
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: FPGA
model sim
power dissipation
speed
universal logic
Opis:: This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.
Źródło:: International Journal of Electronics and Telecommunications; 2019, 65, 3; 477-483
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

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