- Tytuł:
- Design and verification of the chip thermal model: the assessment of a power modules resistance to high current peaks
- Autorzy:
-
Pavlásek, P.
Mrázik, M.
Pavelek, M.
Dobrucký, B. - Powiązania:
- https://bibliotekanauki.pl/articles/377849.pdf
- Data publikacji:
- 2018
- Wydawca:
- Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
- Tematy:
-
power modules
thermal model
simulation
finite element method - Opis:
- The paper is focused on creating a thermal model which provides information about the thermal conditions in the semiconductor devices. Increasing the current density and pressure on prices make the optimization of thermal systems an important part in the design process. Simulation analysis has become with development of computer technology an excellent equipment to achieve it. In creating the model, we take account of material and geometric parameters of bonded chips. By the simulation we obtain the necessary information about the components and thermal stresses, these results can be applied in the device design procedure and technology of production. Resistance to bonded diodes is determined by chip parameters and bonding parameters such as the number of bundles, their spacing, and material. Resistance in practice is determined by experimentally measuring IFSM, a peak permeable, unrepeatable current. Also, in the work we analysed voltage-current VA characteristics of power diodes such as threshold voltage, also the closing voltage we tested functionality and we observe changes in the behaviour of the component and, last but not least, the characteristics of thermal resistance and thermal impedance that served as elements for the construction of an equivalent model. In the next part of the paper, in the context of the works, the methods of bindings of PCB components are currently being extended and used in current technological processes and we also concentrate on the dimensional parameters of the modules used to create an equivalent electrical circuit. The presented assembled simplified model respects the chip size, number of bonding wires, and their layout on the chip. For the concept of nine bonds, we had two types of placement from a variety of bonds, so we also respected this factor in the design of the model. As an example, there is a diode module investigated (SKEE SEMIPACK® 2, 1600V/174A).
- Źródło:
-
Poznan University of Technology Academic Journals. Electrical Engineering; 2018, 95; 57-65
1897-0737 - Pojawia się w:
- Poznan University of Technology Academic Journals. Electrical Engineering
- Dostawca treści:
- Biblioteka Nauki
Artykuł