Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

English (EN)·Polski (PL)·Yкраїнський (UK)
Przejdź do strony domowej biblioteki Centralna Biblioteka Wojskowa Link otwiera się w nowym oknie Logo biblioteki Prolib Integro - strona głównaCentralna Biblioteka Wojskowa

Wyszukujesz frazę "Madhavi, K." wg kryterium: Autor

  Lista filtrów
Wyrównaj
    Wyświetlanie 1-2 z 2
    Tytuł:
    Entropy analysis of third-grade MHD convection flows from a horizontal cylinder with slip
    Autorzy:
    Madhavi, K.
    Prasad, V. R.
    Gaffar, S. A.
    Venkatadri, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/139843.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    third-grade viscoelastic fluid model
    thermal jump
    entropy generation
    Bejan number
    Hartmann number
    lepkosprężysty model cieczy trzeciego stopnia
    skok termiczny
    generowanie entropii
    liczba Bejana
    liczba Hartmanna
    Opis:
    In thermos fluid dynamics, free convection flows external to different geometries, such as cylinders, ellipses, spheres, curved walls, wavy plates, cones, etc., play major role in various industrial and process engineering systems. The thermal buoyancy force associated with natural convection flows can play a critical role in determining skin friction and heat transfer rates at the boundary. In thermal engineering, natural convection flows from cylindrical bodies has gained exceptional interest. In this article, we mathematically evaluate an entropy analysis of magnetohydrodynamic third-grade convection flows from permeable cylinder considering velocity and thermal slip effects. The resulting non-linear coupled partial differential conservation equations with associated boundary conditions are solved with an efficient unconditionally stable implicit finite difference Keller-Box technique. The impacts of momentum and heat transport coefficients, entropy generation and Bejan number are computed for several values of non-dimensional parameters arising in the flow equations. Streamlines are plotted to analyze the heat transport process in a two-dimensional domain. Furthermore, the deviations of the flow variables are compared with those computed for a Newtonian fluid and this has important implications in industrial thermal material processing operations, aviation technology, different enterprises, energy systems and thermal enhancement of industrial flow processes.
    Źródło:
    Archive of Mechanical Engineering; 2018, LXV, 3; 417-440
    0004-0738
    Pojawia się w:
    Archive of Mechanical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Enhanced clock gating technique for power optimization in SRAM and sequential circuit
    Autorzy:
    Ashok Kumar, C.
    Madhavi, B.K.
    Lal Kishore, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/2141882.pdf
    Data publikacji:
    2021
    Wydawca:
    Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
    Tematy:
    enhanced clock gating
    D-Latch gating
    SRAM
    sequential circuit
    Area
    Delay
    Opis:
    Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.
    Źródło:
    Journal of Automation Mobile Robotics and Intelligent Systems; 2021, 15, 2; 32-38
    1897-8649
    2080-2145
    Pojawia się w:
    Journal of Automation Mobile Robotics and Intelligent Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-2 z 2

      Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies