Autor: Ashok Kumar, B - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Phytoremediation of heavy metals from paper mill effluent soil using Croton sparsiflorus
Autorzy:: Ashok Kumar, B
Jothiramalingam, S.
Thiyagarajan, S. K.
Hidhayathullakhan, T.
Nalini, R.
Powiązania:: https://bibliotekanauki.pl/articles/412059.pdf
Data publikacji:: 2014
Wydawca:: Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Tematy:: phytoremediation
heavy metals
effluent soil
croton sparsiflorus
Opis:: Effluents from industries contain appreciable amount of metallic cations like zinc, copper, iron, manganese, lead and cadmium. Release of heavy metal without proper treatment poses a significant threat to public health because of its persistence biomagnifications and accumulation in food chain. To reduce metal pollution problems many processes have been developed for the treatment and disposal of metal containing wastes. Certain plants have the ability to accumulate heavy metals such as Pb, Cr, Cd and Zn. At present, phytoremediation of metals may be approaching commercialization. Hence, possibility can be explored to remove heavy metal load, present even in low concentration, in waste water of paper mill effluent soil by using Croton sparsiflorus.
Źródło:: International Letters of Chemistry, Physics and Astronomy; 2014, 17, 1; 1-9
2299-3843
Pojawia się w:: International Letters of Chemistry, Physics and Astronomy
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Enhanced clock gating technique for power optimization in SRAM and sequential circuit
Autorzy:: Ashok Kumar, C.
Madhavi, B.K.
Lal Kishore, K.
Powiązania:: https://bibliotekanauki.pl/articles/2141882.pdf
Data publikacji:: 2021
Wydawca:: Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
Tematy:: enhanced clock gating
D-Latch gating
SRAM
sequential circuit
Area
Delay
Opis:: Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.
Źródło:: Journal of Automation Mobile Robotics and Intelligent Systems; 2021, 15, 2; 32-38
1897-8649
2080-2145
Pojawia się w:: Journal of Automation Mobile Robotics and Intelligent Systems
Dostawca treści:: Biblioteka Nauki

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