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Tytuł:
Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold
Autorzy:
Kalra, S.
Bhattacharyya, A. B.
Powiązania:
https://bibliotekanauki.pl/articles/226500.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
energy efficiency
ultra-low power
EKV
minimum energy point
minimum delay point temperature to time generator
Opis:
Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 4; 369-374
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Dekompozycja sieci działań układów sekwencyjnych w celu obniżenia poboru mocy
ASM decomposition for low-power design of sequential circuits
Autorzy:
Bułatowa, I.
Salauyou, V.
Matujewicz, P.
Powiązania:
https://bibliotekanauki.pl/articles/155452.pdf
Data publikacji:
2014
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
układ sekwencyjny
pobór mocy
sieć działań
dekompozycja sieci działań
struktura hierarchiczna
low power
sequential circuit
decomposition
partitioning
algorithmic state machine
ASM
hierarchical structure
Opis:
Opracowana została metoda syntezy układów sekwencyjnych o obniżonym poborze mocy, algorytmy sterowania których opisywane są za pomocą sieci działań. Metoda syntezy polega na dekompozycji sieci działań na fragmenty realizowane w postaci oddzielnych automatów połączonych w dwupoziomową strukturę hierarchiczną. Zmniejszenie poboru mocy osiąga się przez odłączenie sygnału synchronizacji od nieaktywnych w danym momencie automatów. Zaproponowano schemat bramkowania sygnału synchronizacji z wykorzystaniem sygnałów struktury hierarchicznej. Opracowany został algorytm dekompozycji sieci działań na fragmenty realizowane jako komponenty struktury hierarchicznej. Przeprowadzone badania potwierdziły efektywność zaproponowanej metody.
In this paper a method for low-power design of hierarchical structures of sequential circuits specified by the Algorithmic State Machine (ASM) charts is presented. The proposed method uses a decomposition of the original sequential circuit into the smaller automata which are connected in a two-level hierarchical structure topology (Fig.1). A clock-gating approach [4, 5] is used to reduce power consumption of the sequential circuit. Due to this approach the power can be saved by clocking only one automaton of hierarchical structure at a time while the clock to the other automata is gated. As a result, only one automaton of hierarchical structure is active at any time while the others are idle, thus reducing the switching activity and minimizing the power dissipation. The algorithm of decomposition of the ASM chart into the fragments, which are implemented as components of a hierarchical structure, has been developed. The clockgating circuit (Fig. 2) which uses the control signals generated by the hierarchical structure is proposed. The power simulation method used to estimate the power consumption for original and decomposed circuits is described. Experimental results show that the proposed partitioning technique can reduce power consumption, on average 20.31%, over the original undecomposed circuit. An additional power saving is available by using special state encoding which reduces the switching activity of sequential circuits.
Źródło:
Pomiary Automatyka Kontrola; 2014, R. 60, nr 7, 7; 501-503
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Weryfikacja czasów obliczeń heurystycznych algorytmów redukcji poboru mocy układów cyfrowych CMOS
Computational time verification of heuristic algorithms forlIow power design of CMOSs circuits
Autorzy:
Szcześniak, W.
Powiązania:
https://bibliotekanauki.pl/articles/268918.pdf
Data publikacji:
2008
Wydawca:
Politechnika Gdańska. Wydział Elektrotechniki i Automatyki
Tematy:
redukcja poboru mocy
cyfrowe układy CMOS
heurystyczne algorytmy redukcji poboru mocy
low power design
digital CMOS circuits
heuristic low power design algorithms
Opis:
W pracy zaprezentowano przeprowadzoną komputerową weryfikację czasów obliczeń piętnastu nowoutworzonych algorytmów heurystycznych dla potrzeb redukcji poboru mocy cyfrowych układów CMOS. W zrealizowanych badaniach eksperymentalnych wykorzystano ogólnodostępne przykłady testowe ISCAS, zaczerpnięte z laboratorium CBL. Uzyskane wyniki pozwalają na akceptację nowoopracowanych algorytmów redukcji poboru mocy układów CMOS z punktu widzenia ich złożoności obliczeniowej.
This paper presents a computer verification of computational complexity of 15 newly elaborated heuristic algorithmsfor low power design of digital CMOS circuits. The verified algorithms were tested against a set of commonly available ISCAS benchmarks from CBL laboratory. The computational complexities of the tested heuristic algorithms were verified experimentally.
Źródło:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej; 2008, 25; 151-154
1425-5766
2353-1290
Pojawia się w:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology
Autorzy:
Abdollahi, Hassan
Hooshmand, Reza
Owlia, Hadi
Powiązania:
https://bibliotekanauki.pl/articles/226818.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
current mode logic (CML)
graphene
graphene FET
low-power design
Opis:
In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 381-388
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Minimalizacja poboru mocy wspólnego modelu automatów skończonych
Minimisation of power dissipation of FSM common model
Autorzy:
Salauyou, V.
Grześ, T.
Powiązania:
https://bibliotekanauki.pl/articles/154327.pdf
Data publikacji:
2009
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
automat skończony
minimalizacja poboru mocy
finite state machine
low power design
Opis:
W artykule przedstawiono nowy algorytm kodowania stanów wewnętrznych automatu skończonego o obniżonym poborze mocy. Zastosowano w nim wspólny model automatu klas ADE co pozwoliło to na zmniejszenie ilości przerzutników przechowujących kod stanu. Badania symulacyjne przeprowadzone z wykorzystaniem standardowych układów testowych potwierdziły skuteczność kodowania z wykorzystaniem proponowanego algorytmu w porównaniu z algorytmami JEDI oraz NOVA, jak i zawartymi we wcześniejszych pracach autorów.
In this paper there is addressed the problem of power minimisation of the finite state machine (FSM). Power reduction is of great importance in design of digital systems as it can improve the speed and extend the time between recharging the batteries in mobile systems. In the common model of the FSM of class ADE (Section 2) the set A of internal states consists of three subsets: AA, AD, and AE. AA is the set of internal states of the FSM of class A, AD is the set of internal states of the FSM of class D (the output vector is identical to the next state code), and AE is the set of internal states of the FSM of class E (the input vector is identical to the next state code) [12]. The common model of the FSM of class ADE requires an additional register used for storing the input and output vector values. These registers are present in modern programmable logic devices. In Section 3 there is proposed a new algorithm of the FSM state assignment that makes use of the common model. The assigned code consists of three parts: G - input vector, Z - output vector and E - state code. G and Z are stored in the input and output registers, respectively. With this algorithm it is possible to assign codes that are shorter than those assigned with use of classical methods, and thus less power is dissipated in registers storing the current state code during every transition. The experimental results (Section 4, Tables 1 and 2) show the significant reduction (of 13 to 51%) in power dissipation compared to classic (JEDI, NOVA, column-based) and recent (sequential and iterating) algorithms.
Źródło:
Pomiary Automatyka Kontrola; 2009, R. 55, nr 7, 7; 491-493
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Badania algorytmów kodowania stanów wewnętrznych automatu skończonego zorientowanych na minimalizację poboru mocy
Exploration of the Low Power Oriented Algorithms of the Finite State Machines State Assignment
Autorzy:
Salauyou, V.
Grześ, T.
Powiązania:
https://bibliotekanauki.pl/articles/156218.pdf
Data publikacji:
2008
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
automat skończony
kodowanie
minimalizacja poboru mocy
finite state machine
state assignment
low power design
Opis:
Kodowanie stanów wewnętrznych automatu skończonego jest jednym z ważniejszych procesów podczas syntezy automatu. W artykule skoncentrowano się na algorytmach minimalizujących pobór mocy. Przeprowadzono badania algorytmu kodowania kolumnowego oraz dwóch algorytmów opracowanych przez autorów: sekwencyjnego oraz iteracyjnego. Wyniki badań wykazują znaczące zmniejszenie poboru mocy układów zakodowanych z wykorzystaniem algorytmu sekwencyjnego w porównaniu z algorytmem kodowania kolumnowego (średnio o 12%), natomiast zastosowanie algorytmu iteracyjnego pozwoliło na obniżenie mocy średnio o kolejne 2% (w porównaniu do algorytmu sekwencyjnego).
Finite State Machine (FSM) state assignment is one of the most important activities during the synthesis. In this paper we focused on the low-power design oriented algorithms. We explore column-based algorithm as well as two algorithms researched by authors: sequential and iterational. Experimental results shows the significant reduction of the power dissipation after state assignment using sequential algorithm in comparison with the column-based algorithm (of about 12%). Iterational algorithm increase power reduction of about 2% (in comparison with the sequential algorithm).
Źródło:
Pomiary Automatyka Kontrola; 2008, R. 54, nr 8, 8; 499-501
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Algorytmy kodowania stanów wewnętrznych automatu skończonego do minimalizacji poboru mocy
Finite state machines state assignment algorithms for power minimization
Autorzy:
Grześ, T.
Salauyou, V.
Powiązania:
https://bibliotekanauki.pl/articles/341129.pdf
Data publikacji:
2008
Wydawca:
Politechnika Białostocka. Oficyna Wydawnicza Politechniki Białostockiej
Tematy:
automat skończony
kodowanie stanów
obniżanie poboru mocy
finite state machine
state assignment
low power design
Opis:
Kodowanie stanów wewęetrznych automatu skończonego jest jednym z ważniejszych procesów podczas syntezy automatu. Zastosowanie odpowiedniego algorytmu pozwala m.in. obnizyć pobór mocy. W artykule skoncentrowano się na algorytmach minimalizujących pobór mocy. Przeprowadzono badania nad algorytmem kodowania kolumnowego, opisanego w pracy [1] oraz nad dwoma algorytmami opracowanymi przez autorów: sekwencyjnym [7] oraz rafinacyjnym. Badania przeprowadzono na standardowych układach testowych, opracowanych w Microelectronics Center of North Carolina [9]. Wyniki badań wykazują znaczące zmniejszenie poboru mocy układów zakodowanych z wykorzystaniem algorytmu sekwencyjnego w porównaniu z poborem z wykorzystaniem algorytmu kodowania kolumnowego (średnio o 12%); zastosowanie algorytmu rafinacyjnego pozwoliło obniżyć moc średnio o kolejny 1%.
State assignment for a finite state machine (FSM) is an important process in logic synthesis of the sequential circuits in programmable devices. Using the proper algorithm provides among other things the reduction of the power dissipation. In this paper we focused on the algorithms that reduce power dissipation. The analysis of the column based algorithm (described in [1]) as well as two algorithms proposed by authors: sequential [7] and iterational was made. Experiments were made on standard benchmarks, researched in Microelectronics Center of North Carolina [9]. Obtained results showed significant reduction of the power dissipation when using the sequential algorithm (12% in comparison with the column-based algorithm). Iterational algorithm improves the results by additional 1%.
Źródło:
Zeszyty Naukowe Politechniki Białostockiej. Informatyka; 2008, 3; 53-66
1644-0331
Pojawia się w:
Zeszyty Naukowe Politechniki Białostockiej. Informatyka
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low-Power High-Speed Double Gate 1-bit Full Adder Cell
Autorzy:
Kumar, R.
Roy, S.
Bhunia, C. T.
Powiązania:
https://bibliotekanauki.pl/articles/226653.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
low-power full-adder
low-power CMOS design
multiplexer based full-adder design
multi-threshold voltage based full-adder design
pass transmission logic
Opis:
In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 4; 329-334
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A solution to low power switched capacitor integrator design with reduced effective input capacitance
Autorzy:
Korkmaz, S.
Dundar, G.
Powiązania:
https://bibliotekanauki.pl/articles/398106.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
integrator małej mocy
bardzo duża stała czasowa integratora
skuteczne zmniejszenie pojemności
włączony integrator kondensatora
low power integrator
very large time constant integrator
effective capacitance reduction
switched capacitor integrator
Opis:
A novel low power Switched Capacitor Integrator with reduced effective input capacitance is proposed in this paper. It is mainly based on reducing the effective input sampling capacitance by charge sharing with an extra capacitance, such that the integration capacitance can be chosen much smaller while maintaining the same sampling to integration capacitance ratio. Reducing the integration capacitance will result in less integration current and less integration current will in turn result in less power over the integrator which is the main goal of this work, reducing the integrator power consumption and chip area. Another main advantage of this configuration is, that it can be used in large time constant integrators without using physically large integration capacitance.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 3; 229-235
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of Low Power Low Voltage Bulk Driven Operational Transconductance Amplifier (BD-OTA)
Autorzy:
Shaktour, M. A.
Powiązania:
https://bibliotekanauki.pl/articles/377604.pdf
Data publikacji:
2014
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
Bulk-driven transistors
low-voltage
low-power OTA
PSpice simulation
Opis:
Operational Transconductance Amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Here we design Low Power Low Voltage Bulk Driven OTA with a new concept of high-linearity OTA with controllable Transconductance is proposed. The OTA is simulated in a standard TSMC 0.18 mm CMOS process with a 0.6 V supply voltage.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 63-69
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Low Power and High Performance Hardware Design for Automatic Epilepsy Seizure Detection
Autorzy:
Rafiammal, S. Syed
Najumnissa, D.
Anuradha, G.
Mohideen, S. Kaja
Jawahar, P. K.
Mutalib, Syed Abdul
Powiązania:
https://bibliotekanauki.pl/articles/963923.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
epilepsy detection
system on chip
implementation
Quadrature Linear Discriminant Analysis
hardware design
seizure detection
Opis:
An application specific integrated design using Quadrature Linear Discriminant Analysis is proposed for automatic detection of normal and epilepsy seizure signals from EEG recordings in epilepsy patients. Five statistical parameters are extracted to form the feature vector for training of the classifier. The statistical parameters are Standardised Moment, Co-efficient of Variance, Range, Root Mean Square Value and Energy. The Intellectual Property Core performs the process of filtering, segmentation, extraction of statistical features and classification of epilepsy seizure and normal signals. The design is implemented in Zynq 7000 Zc706 SoC with average accuracy of 99%, Specificity of 100%, F1 score of 0.99, Sensitivity of 98% and Precision of 100 % with error rate of 0.0013/hr., which is approximately zero false detection.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 707-712
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of low power analog front-end for 13.56MHz RFID transponder
Autorzy:
Saleh, S.
Osman, M.
Hamdy, G.
Zaki, A.
Elsemary, H.
Powiązania:
https://bibliotekanauki.pl/articles/397985.pdf
Data publikacji:
2017
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
analog front frond
RFID
charge pump
OOK
pompa zasilająca
Opis:
This paper presents the design of 13.56MHz RF Front-end circuit for low-power medical applications. It converts RF power into DC and then extracts the clock and the data. The design includes rectifier, voltage multiplier, voltage regulator, data demodulator, ring oscillator, RF voltage limiter and LC matching network. It provides an excellent trade-off between high performance, simplicity of architecture, and low power consumption. It is designed to be fully integrated on chip. Simulation is done using 0.35-μm CMOS technology and the results are compared with other reported RFID systems. The total power consumption is adjusted to be around 4 μW at the minimum input power.
Źródło:
International Journal of Microelectronics and Computer Science; 2017, 8, 4; 146-149
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process
Autorzy:
Shylu Sam, D. S.
Sam Paul, P.
Jeba Jingle, Diana
Mano Paul, P.
Samuel, Judith
Reshma, J.
Sudeepa, P. Sarah
Evangeline, G.
Powiązania:
https://bibliotekanauki.pl/articles/2124770.pdf
Data publikacji:
2022
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
flash ADC
low power
dynamic comparator
encoder
Opis:
This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
Źródło:
International Journal of Electronics and Telecommunications; 2022, 68, 3; 565--570
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of broadband power line communication module for automatic meter reading
Autorzy:
Chen, Xia
Liu, Ling
Powiązania:
https://bibliotekanauki.pl/articles/949869.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
automatic meter reading
low-power consumption
long-distance transmission
power line communication
Opis:
Low-power consumption and long-distance transmission are two problems that have to be solved by the application of broadband power line communication for the automatic meter reading system. To reduce the power consumption of the communication module, based on the analysis of the composition of the power consumption, some methods are proposed. From the communication chip level and the module circuit level, the design scheme of low-power consumption is given. To solve the problem of transmission distance, a frequency band of 2.44 MHz~5.6 MHz is used as the main working frequency band. The communication module supports multiple frequency bands. Using this feature, the optimal frequency band is adaptively selected for communication and automatic switching, which further improve the transmission distance. Field application shows that the above methods effectively decrease the power consumption of the communication module and extend the transmission distance.
Źródło:
Archives of Electrical Engineering; 2020, 69, 4; 771-780
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The Design Aspects for Ultra Low-Power, Low-Noise 90 nm CMOS Charge Sensitive Amplifier for the Active Pixel Detector
Autorzy:
Barzdenas, V.
Navickas, R.
Powiązania:
https://bibliotekanauki.pl/articles/1807954.pdf
Data publikacji:
2009-06
Wydawca:
Polska Akademia Nauk. Instytut Fizyki PAN
Tematy:
84.37.+q
07.77.Ka
Opis:
A falling particle in the digital registration systems for elementary particles active pixel detector induces electric charge, the value of which describes the parameters of the particle in the detector. Since the electric charge induced by a single particle is relatively weak, the detector signal is first processed (amplified and shaped) right in the zone of irradiation and only then transmitted further. This paper analyses the primary analogical registration electronics for digital registration systems for elementary particles active pixel detectors, which is charge sensitive amplifiers operating in the nanoampere region.
Źródło:
Acta Physica Polonica A; 2009, 115, 6; 1139-1140
0587-4246
1898-794X
Pojawia się w:
Acta Physica Polonica A
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and testing of a low cost peak-power tracking controller for a fixed blade 1.2 kVA wind turbine
Autorzy:
Gitano, H.
Taib, S.
Khdeir, M.
Powiązania:
https://bibliotekanauki.pl/articles/262657.pdf
Data publikacji:
2008
Wydawca:
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie
Tematy:
wind turbine
DC-DC converter
peak power tracking
power controller
Opis:
Wind turbines are a common source of electrical power generation in rural sites around the world. The power generated by a wind turbine at a given wind speed is a non-linear function of rotor speed. This results in a specific rotor speed for maximum power production at each wind speed. A control system incorporating a Pulse Width Modulated DC -DC converter has been designed to vary the load on the wind turbine thereby forcing it to operate at its maximum power point. Another important feature of the controller is the application of electrical stall-breaking of the turbine. The circuit was then tested on a turbine test bed simulating various wind speeds, and the “peak-power tracking” capability and electrical breaking capability were verified. The system gave an overall efficiency of 70 to 80% over a wide range of wind speeds and PWM duty cycles.
Źródło:
Electrical Power Quality and Utilisation. Journal; 2008, 14, 1; 95-101
1896-4672
Pojawia się w:
Electrical Power Quality and Utilisation. Journal
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation
Autorzy:
Wang, Y.
Cai, H.
Powiązania:
https://bibliotekanauki.pl/articles/226202.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
cardiac pacemaker
CMOS
ultra-low power
analogue-to-digital
Sigma-Delta modulation
continuous-time
Opis:
A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².
Źródło:
International Journal of Electronics and Telecommunications; 2014, 60, 1; 109-115
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multiobjective Design of Wireless Ad Hoc Networks: Security, Real-Time and Lifetime
Autorzy:
Zdravko, K.
Powiązania:
https://bibliotekanauki.pl/articles/308972.pdf
Data publikacji:
2009
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
ad hoc networks
low-power routing
multihop communication
secure routing
Opis:
This paper deals with the tradeoffs between security, real-time and lifetime performance. Due to the multihop nature of communication wireless ad hoc networks are very vulnerable to attacks. Malicious nodes included in a routing path may misbehave and organize attacks such as black holes. Scaling the number of hops for a packet delivery we trade off energy efficiency against security and real-time communication. To study the multihop communication we propose a hierarchical communication model. The REWARD (receive, watch, redirect) algorithm for secure routing is employed as a main example for corrective actions. Symmetrical routing is a distinguish feature of protocols such as REWARD and we outline the threshold of conflict between power-efficient partitioning of communication links and symmetrical routing.
Źródło:
Journal of Telecommunications and Information Technology; 2009, 2; 13-21
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and Noise Analysis of a Novel Auto-Zeroing Structure for Continuous-Time Instrumentation Amplifiers
Autorzy:
Maréchal, S.
Nys, O.
Krummenacher, F.
Chevroulet, M.
Kayal, M.
Powiązania:
https://bibliotekanauki.pl/articles/226106.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
front-end
instrumentation amplifier
low-noise
low power
chopper
auto-zero
Opis:
This paper introduces a low-noise, low-power amplifier for high-impedance sensors. An innovative circuit using an auto-zeroed architecture combined with frequency modulation to reject offset and low-frequency noise is proposed and analysed. Special care was given to avoid broadband noise aliasing and chopping in the signal path, and to minimize both the resulting equivalent input offset voltage and equivalent input biasing current. The theoretical noise analysis of the proposed topology covers most of the noise sources of the circuit. Simulations show that the input-referred noise level of the circuit is 13.4nV/√Hz for a power consumption of 85µA with a power supply from 1.8V to 3.6V.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 397-404
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and evaluation of a low-cost solar simulator and measurement system for low-power photovoltaic panels
Autorzy:
Walczak, Marcin
Bychto, Leszek
Kraśniewski, Jarosław
Duer, Stanisław
Powiązania:
https://bibliotekanauki.pl/articles/2173895.pdf
Data publikacji:
2022
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
solar simulator
photovoltaic panels
photovoltaics
measurements of PV panel characteristics
MPPT evaluation
Opis:
Research related to photovoltaic panels comprises different topics starting with modelling solar cells, finding new maximum power point tracking (MPPT) algorithms, testing existing ones or designing of DC/DC converters for MPPT systems and microgrids that incorporate photovoltaic energy sources. In each of the examples above a deep knowledge of photovoltaic panels is required, as well as a reliable measurement system that can deliver continuous, stable light with enough power to meet standard test conditions (STC) and that can ensure repeatable results. Therefore this paper presents a low-cost solar simulator with a microcontroller-based measurement system, that can be used for various measurements of low-power photovoltaic panels.
Źródło:
Metrology and Measurement Systems; 2022, 29, 4; 685--700
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
International standardization in the design of “Shore To Ship” - power supply systems of ships in port
Autorzy:
Tarnapowicz, D.
German-Galkin, S.
Powiązania:
https://bibliotekanauki.pl/articles/410120.pdf
Data publikacji:
2018
Wydawca:
STE GROUP
Tematy:
Shore to Ship system
High Voltage Shore Connection
Low Voltage Shore Connection
Opis:
The decisive source of air pollution emissions in ports is the berthed ships. This is primarily caused by the work of ship’s autonomous generator sets. One way of reducing the air pollution emissions in ports is the supply of ships from electricity inland system. The main problem connected with the power connection of ships to the inland network is caused by different values of levels and frequencies of voltages in these networks (in various countries) in relation to different values of levels and frequencies of voltages present in the ship’s network. It is also important that the source power can range from a few hundred kW up to several MW. In order to realize a universal „Shore to Ship” system that allows the connection of ships to the electricity inland network, the international standardization is necessary. This article presents the current recommendations, standards and regulations for the design of „Shore to Ship” systems.
Źródło:
Management Systems in Production Engineering; 2018, 1 (26); 9-13
2299-0461
Pojawia się w:
Management Systems in Production Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Wolnoobrotowy generator z magnesami trwałymi do elektrowni wiatrowej z turbiną o pionowej osi obrotu
Low speed permanent magnet generator for vertical axis wind turbine
Autorzy:
Kostro, G.
Kutt, F.
Michna, M.
Ronkowski, M.
Powiązania:
https://bibliotekanauki.pl/articles/269128.pdf
Data publikacji:
2016
Wydawca:
Politechnika Gdańska. Wydział Elektrotechniki i Automatyki
Tematy:
mała elektrownia wiatrowa
generator
magnesy trwałe
projektowanie
low power vertical
axis wind turbine
permanent magnet generator
design
Opis:
W artykule przedstawiono założenia projektowe, wybrane wyniki etapu projektowania i badania prototypu wolnoobrotowego generatora z magnesami trwałymi współpracującego z elektrownią wiatrową z innowacyjną turbiną o pionowej osi obrotu. Projekt został wykonany na zlecenie firmy ALU ECO Sp. z o.o. z Gdańska w ramach projektu badawczorozwojowego Pionowa Turbina Wiatrowa, współfinansowanego przez Polską Agencję Rozwoju Przedsiębiorczości ze środków programu Wsparcie w ramach dużego bonu. Zaprojektowano, wykonano i zbadano prototyp generatora prądu przemiennego o mocy 15 kVA i napięciu znamionowym 400 V przy prędkości 95 obr/min. Generator może znaleźć zastosowanie w energetyce wiatrowej małej mocy, w tym na jednostkach pływających (statkach, jachtach) oraz w stacjonarnych instalacjach prosumenckich.
The paper presents the design of the low speed permanent magnet generator for the innovative vertical axis wind turbine. The paper shows the design assumption, selected results from the design stage and the prototype testing stage. The project was commissioned by the company ALU ECO Sp. o.o. Gdansk and co-financed by the Polish Agency for Enterprise Development. The power of the prototype generator is 15kVA and the rated voltage is 400V at a speed of 95 rpm. The generator can be used in low-power wind energy, including on vessels (ships, yachts) and in the stationary installations.
Źródło:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej; 2016, 50; 33-37
1425-5766
2353-1290
Pojawia się w:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Co-design of a low-power RF receiver and piezoelectric energy harvesting power supply for a Wireless Sensor Node
Autorzy:
Mancelos, N
Correia, J
Oliveira, J. P.
Oliveira, L. B.
Powiązania:
https://bibliotekanauki.pl/articles/398018.pdf
Data publikacji:
2014
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
CMOS RF analog front-end
low-voltage wideband balun LNA
passive mixer
piezoelectric energy harvesting
active full bridge rectifier
LDO regulator
układ analogowy CMOS
balun szerokopasmowy
mikser pasywny
energia piezoelektryczna
prostownik aktywny
prostownik mostkowy
regulator LDO
Opis:
A low-voltage RF CMOS receiver front-end and an energy harvesting power circuit for a piezoelectric source are presented as a co-designed solution for a Wireless Sensor Node. A MOSFET-only Wideband balun LNA with noise cancelling and a 0.6 V supply voltage is designed in conjunction with a passive mixer. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver front-end reaches a total voltage conversion gain of 31 dB, a 0.1-5.2 GHZ bandwidth, an IIP3 value of -1.35 dBm, and a noise figure inferior to 9 dB. The total power consumption is 1.95 mW. The energy harvesting power circuit consists of an active full bridge cross-coupled rectifier followed by a low-dropout (LDO) regulator, and it is able to guarantee a power output of 6 mW with a regulated output voltage of 0.6 V, for typical vibration patterns.
Źródło:
International Journal of Microelectronics and Computer Science; 2014, 5, 4; 136-143
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Stabilizer design of PSS3B based on the KH algorithm and Q-Learning for damping of low frequency oscillations in a single-machine power system
Autorzy:
Mohamadi, Farshid
Sedaghati, Alireza
Powiązania:
https://bibliotekanauki.pl/articles/41190034.pdf
Data publikacji:
2023
Wydawca:
Politechnika Warszawska, Instytut Techniki Cieplnej
Tematy:
3-band power system stabilize
reinforcement learning
Q-learning
system zasilania
uczenie przez wzmacnianie
Opis:
The aim of this study is to use the reinforcement learning method in order to generate a complementary signal for enhancing the performance of the system stabilizer. The reinforcement learning is one of the important branches of machine learning on the area of artificial intelligence and a general approach for solving the Marcov Decision Process (MDP) problems. In this paper, a reinforcement learning-based control method, named Q-learning, is presented and used to improve the performance of a 3-Band Power System Stabilizer (PSS3B) in a single-machine power system. For this end, we first set the parameters of the 3-band power system stabilizer by optimizing the eigenvalue-based objective function using the new optimization KH algorithm, and then its efficiency is improved using the proposed reinforcement learning algorithm based on the Q-learning method in real time. One of the fundamental features of the proposed reinforcement learning-based stabilizer is its simplicity and independence on the system model and changes in the working points of operation. To evaluate the efficiency of the proposed reinforcement learning-based 3-band power system stabilizer, its results are compared with the conventional power system stabilizer and the 3-band power system stabilizer designed by the use of the KH algorithm under different working points. The simulation results based on the performance indicators show that the power system stabilizer proposed in this study underperform the two other methods in terms of decrease in settling time and damping of low frequency oscillations.
Źródło:
Journal of Power Technologies; 2023, 103, 4; 230-242
1425-1353
Pojawia się w:
Journal of Power Technologies
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design Sensitivity Studies on a Hydroacoustic Projector Using an Experimentally Validated Easy-to-Build Model
Autorzy:
Sreejith, Vattaparambil Sreedharan
Tiwari, Nachiketa
Powiązania:
https://bibliotekanauki.pl/articles/2141678.pdf
Data publikacji:
2022
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
low frequency sound source
underwater transducer
fluid power
hydro-electro-mechano-acoustic analogy
hydraulic valve
piston
cylinder
Opis:
Hydroacoustic projectors are useful for generating low frequency sounds in water. Existing works on hydroacoustic projectors require two significant enhancements, especially for designers. First, we need to understand the influence of important projector design parameters on its performance. Such insights can be very useful in developing a compact and efficient projector. Second, there is a need for an integrated model of the projector based on easily available and user-friendly numerical tools which do not require development of complex customised mathematical analogs of projector components. The present work addresses both such needs. Towards these goals, an experimentally validated, easy-to-build projector model was developed and used to conduct design sensitivity studies. We show that reductions in pipe compliance and air content in oil, and an increase in orifice discharge coefficient can yield remarkable improvements in projector’s SPL. We also show that reductions in pipe length and cylinder diameter cause moderate improvements in performance in mass and stiffness controlled regions, respectively. In contrast, the projector performance is insensitive to changes in pistonic mass, cylinder length, and diaphragm stiffness. Finally, we report that while pipe compliance and air content in oil can sharply alter system resonance, the effects of changes in pipe length and pistonic mass on it are moderate in nature.
Źródło:
Archives of Acoustics; 2022, 47, 1; 113-124
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-25 z 28

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