Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

English (EN)·Polski (PL)·Yкраїнський (UK)
Przejdź do strony domowej biblioteki Centralna Biblioteka Wojskowa Link otwiera się w nowym oknie Logo biblioteki Prolib Integro - strona głównaCentralna Biblioteka Wojskowa

Wyszukujesz frazę "CMOS Technology" wg kryterium: Wszystkie pola

  Lista filtrów
Wyrównaj
Wyświetlanie 1-15 z 17
Tytuł:
A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
Autorzy:
Khatak, Anil
Kumar, Manoj
Dhull, Sanjeev
Powiązania:
https://bibliotekanauki.pl/articles/1844527.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog to digital converter
ADC
successive approximation register (SAR)
common mode current feedback gain boosting
CMFD-GB
residue amplifier
RA
spurious free dynamic range
SFDR
integral nonlinearity
INL
differential nonlinearity
DNL
Opis:
A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and analysis of MOS based Magnetic Field Sensor
Autorzy:
Kumar, Rakesh
Powiązania:
https://bibliotekanauki.pl/articles/1075557.pdf
Data publikacji:
2019
Wydawca:
Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
Tematy:
CMOS Technology
Hall Effect
Lorentz force
MagFET device
Magnetic sensor
Opis:
Magnetic sensors are widely used in various applications such as consumer electronic products (mobile phones, laptops), biomedical applications (brain function mapping), navigation, vehicle detection, mineral prospecting, non-contact switching (keyboard), contactless temperature measurement, wireless sensor network etc. Sensitivity of MagFET devices towards magnetic field, depends on the shape, dimensions VGS, VDS. In this paper we have measured effect of Physical design of gate on sensitivity of MagFET.
Źródło:
World Scientific News; 2019, 121; 42-47
2392-2192
Pojawia się w:
World Scientific News
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A High-Efficient Low-Voltage Rectifier for CMOS Technology
Autorzy:
Jendernalik, W.
Jakusz, J.
Blakiewicz, G.
Kłosowski, M.
Powiązania:
https://bibliotekanauki.pl/articles/220356.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS rectifier
high frequency rectifier
wireless power transmission
Opis:
A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages.
Źródło:
Metrology and Measurement Systems; 2016, 23, 2; 261-268
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A low-jitter, full-differential PLL in 0.18μm CMOS technology
Autorzy:
Modarresi, F.
Ghasemzadeh, M.
Mazlumi, M.
Amini, A.
Abolfathi, T.
Powiązania:
https://bibliotekanauki.pl/articles/397765.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
full differential PLL
PFD
VCO
low jitter
CPL
pętla synchronizacji fazy
PLL
generator sterowany napięciem
niski jitter
Opis:
This paper presents a Phase Locked Loop (PLL) which works with minimum jitter in the operation frequency range of 600MHZ to 900MHZ. Utilizing a full differential architecture that consists of several blocks of differential VCO, a differential PFD and a differential CPL leads to limiting the RMS jitter to 4.06ps, with 50mV power supply noise in the frequency range of 750MHz. Simulation results using 0.18μm CMOS TSMC standard technology demonstrate the power-consumption of 4.6mW at the supply voltage of 1.8V.
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 4; 119-122
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multiple output CMOS current amplifier
Autorzy:
Pankiewicz, B.
Powiązania:
https://bibliotekanauki.pl/articles/201141.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
current amplifier
current follower
current mirror
CMOS technology
wzmacniacz prądowy
prąd
technologia CMOS
Opis:
In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 301-306
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology
Autorzy:
Bellizia, D.
Scotti, G.
Trifiletti, A.
Powiązania:
https://bibliotekanauki.pl/articles/398086.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
IoT
internet of things (IoT)
Power Analysis Attacks
smart card
CPA
current-mode
Side Channel Analysis
CMOS
Cryptography
PRESENT
Internet rzeczy
karta inteligentna
moduły prądowe
kryptografia
Opis:
The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 4; 147-156
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals
Autorzy:
Bhuiyan, M. A.
Reaz, M. B. I.
Jalil, J.
Rahman, L. F.
Powiązania:
https://bibliotekanauki.pl/articles/200508.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS
ISM band
nanometer
transceivers
T/R switch
wireless
Opis:
This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 μW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125°C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2014, 62, 2; 399-406
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Designing Method of Compact n-to-2ⁿ Decoders
Autorzy:
Brzozowski, I.
Zachara, Ł.
Kos, A.
Powiązania:
https://bibliotekanauki.pl/articles/226116.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
decoder
address decoder
standard cell
layouts design
CMOS technology
power dissipation
power consumption
delay
Opis:
What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to-2ⁿ -lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 405-413
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 žm CMOS technology
Autorzy:
Jendernalik, W.
Jakusz, J.
Blakiewicz, G.
Szczepański, S.
Piotrowski, R.
Powiązania:
https://bibliotekanauki.pl/articles/220599.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS imager
analogue processor array
smart sensor
vision chip
Opis:
The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.
Źródło:
Metrology and Measurement Systems; 2012, 19, 2; 191-202
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
64 channel neural recording amplifier with tunable bandwidth in 180 nm CMOS technology
Autorzy:
Gryboś, P.
Kmon, P.
Żołądź, M.
Szczygieł, R.
Kachel, M.
Lewandowski, M.
Błasiak, T.
Powiązania:
https://bibliotekanauki.pl/articles/220527.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
neurobiological measurements
low noise amplifier
neural recording
band-pass filter
multichannel ASIC
Opis:
This paper presents the design and measurements of low-noise multichannel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and is fabricated in CMOS 180 nm technology. A single readout channel is built of an AC coupling circuit at the input, a low-noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and good matching performance and has the possibility of passband tuning. The low cut-off frequency can be tuned in the 1 Hz - 60 Hz range while the high cut-off frequency can be tuned in the 3.5 kHz - 15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 žW, the equivalent input noise is in the range from 6 žV - 11 žV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of the gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency set at 1.6 Hz is only 0.07 Hz. The chip occupies 5×2.3 mm⊃2 of silicon area. To our knowledge, our solution is the first reported multichannel recording system which allows to set in each recording channel the low cut-off frequency within a single Hz with a small spread of this parameter from channel to channel. The first recordings of action potentials from the thalamus of the rat under urethane anesthesia are presented.
Źródło:
Metrology and Measurement Systems; 2011, 18, 4; 631-643
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
Autorzy:
Kushwaha, P.
Chaudhry, A.
Powiązania:
https://bibliotekanauki.pl/articles/308384.pdf
Data publikacji:
2011
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
5T SRAM
65 nm CMOS technology
6T SRAM
7T SRAM
low power SRAM
power reduction technique
Opis:
In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
Źródło:
Journal of Telecommunications and Information Technology; 2011, 4; 124-130
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis and optimization of LUDMOS transistors on a 0.18um SOI CMOS technology
Autorzy:
Toulon, G.
Cortés, I.
Morancho, F.
Villard, B.
Powiązania:
https://bibliotekanauki.pl/articles/397849.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
moc MOSFET
LDMOS
RESURF
STI (płytki rów izolacyjny)
krzem na izolatorze
power MOSFET
STI (shallow trench isolation)
superjunction
silicon-on-insulator
Opis:
This paper is focused on the design and optimization of power LDMOS transistors (V br > 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 μm SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (Ron-sp/Vbr tradeoff) and dynamic (Miller capacitance and QgxRon FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 1; 3-8
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Projekt kompensacyjnego przetwornika analogowo-cyfrowego dla potrzeb wielokanałowych układów w technologii submikronowej
Project of successive approximation analog-to-digital converter for multichannel circuits in submicron technology
Autorzy:
Otfinowski, P.
Zaziąbł, A.
Powiązania:
https://bibliotekanauki.pl/articles/158172.pdf
Data publikacji:
2010
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
przetwornik analogowo-cyfrowy z równoważeniem ładunku
klucze CMOS
analog-to-digital converter
charge redistribution
successive approximation
CMOS switch
Opis:
W pracy zaprezentowano projekt scalonego przetwornika analogowo-cyfrowego wykonany w technologii UMC CMOS 180nm. Przedstawiono rozwiązanie pozwalające na znaczące zmniejszenie powierzchni zajmowanej przez układ poprzez dodanie pomocniczego przetwornika C/A. Zostało przybliżone także zagadnienie odpowiedniego doboru kluczy w układach z przełączanymi pojemnościami. Ostatecznie zaprezentowany układ cechuje się szybkością konwersji wynoszącą 3 MS/s przy poborze mocy 225 žW oraz bardzo niską nieliniowością.
The dynamic progress in the domain of applications involving X rays demands more sophisticated circuits for acquisition and processing of signals from the silicon detectors. This paper presents a design of an integrated analog-to-digital converter dedicated to multichannel silicon detector readout circuits. The successive approximation with charge redistribution architecture was proposed. In order to reduce the total chip area, the DAC was split into two blocks. The capacitor array used as a primary DAC and also as a sampling circuit. As a secondary DAC, the resistive voltage divider was introduced. This solution allowed reducing the total DAC area by the factor of 6, maintaining the same output voltage accuracy. The CMOS switches are described in detail, as they play important role in the switch capacitor circuits, affecting both the speed and accuracy of the primary capacitive DAC. A synchronous regenerative latch is used as a comparator. The ADC is implemented in UMC CMOS 180nm technology. The designed ADC is able to achieve conversion rates of 3 MS/s at 225 žW. The final simulation results show also low nonlinearity of the presented circuit.
Źródło:
Pomiary Automatyka Kontrola; 2010, R. 56, nr 10, 10; 1209-1212
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Projekt scalonego wzmacniacza ładunkowego na potrzeby przetwarzania typu Time-over-Threshold
Design of the integrated charge-sensitive amplifier for the Time-over-Threshold based processing
Autorzy:
Kasiński, K.
Szczygieł, R.
Powiązania:
https://bibliotekanauki.pl/articles/157771.pdf
Data publikacji:
2010
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
układ scalony
technologia CMOS
krzemowy detektor paskowy Time-over-Threshold
wzmacniacz ładunkowy
integrated circuit
CMOS technology
silicon strip detector
Time-over-Threshold
charge sensitive amplifier
CSA
Opis:
Praca przedstawia projekt scalonego wzmacniacza ładunkowego zaprojektowanego dla aplikacji w układzie do odczytu detektorów paskowych w eksperymencie fizyki wysokich energii wykorzystującego przetwarzanie typu Time-over-Threshold. Zastosowane rozwiązania zostały zapożyczone z układów pikselowych. Projekt wykonano dla technologii United Microelectronics Corporation 180 nm. Zaprojektowany wzmacniacz charakteryzuje się niskim poborem mocy, niskimi szumami a także bardzo szerokim zakresem liniowej pracy zachowując swoje właściwości dla obu polarności ładunków wejściowych.
New High Energy Physics experiments require new and better solutions for the detector readout systems. This paper presents the project of the charge sensitive amplifier (CSA) for the silicon strip detector readout chip implementing the Wilkinson-type analog to digital converter (called also Time-over-Threshold processing). This allows to implement the reasonable resolution and speed ADC in each channel while keeping the overall power consumption low. This is due to the fact that the information about the input charge is kept in the CSA output pulse length and can be then easily converted to digital domain. It has been designed for the UMC (United Micro-electronics Corporation) 180nm technology and should fit into 50 Μm pitch channel slot. Some solutions were adapted from the pixel-oriented integrated circuits and are optimized for much higher detec-tor capacitances. Presented charge sensitive amplifier shows very high dynamic range - much higher than required 0-16 fC. The dynamic range is not limited by the dynamic range of the amplifier itself which is a feature of the implemented discharge circuit. The processing chain has an ability to operate for both holes and electrons while keeping the low power consumption (625 ΜW) and low noise (720 e- at 30 pF detector capacitance). The paper presents the simulation-based performance of the circuit.
Źródło:
Pomiary Automatyka Kontrola; 2010, R. 56, nr 9, 9; 1043-1046
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
Autorzy:
Bieniek, T.
Beck, R. B.
Jakubowski, A.
Głuszko, G.
Konarski, P.
Ćwil, M.
Powiązania:
https://bibliotekanauki.pl/articles/308685.pdf
Data publikacji:
2007
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
CMOS
dual gate oxide
gate stack
oxynitride
plasma implantation
Opis:
The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
Źródło:
Journal of Telecommunications and Information Technology; 2007, 3; 3-8
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 17

Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies