Autor: Sallese, J.-M. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Hall effect sensors performance investigation using three-dimensional simulations
Autorzy:: Paun, M.-A.
Sallese, J.-M.
Kayal, M.
Powiązania:: https://bibliotekanauki.pl/articles/398136.pdf
Data publikacji:: 2011
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: hallotron
wygładzanie numeryczne
symulacja fizyczna
symulacja 3D
hall effect sensor
numerical offset
numerical drift
3D physical simulations
Opis:: Several Hall effect sensors were modeled and evaluated regarding the Hall voltage and sensitivity using 3D physical simulations. For accurate results the numerical offset and its temperature drift were analyzed. The versatility of the simulation allows various Hall sensor implementations. The simulation procedure could guide the designer in choosing the Hall cell optimum fabrication process, shape and dimensions in terms of the performances envisaged to be achieved.
Źródło:: International Journal of Microelectronics and Computer Science; 2011, 2, 4; 140-145
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Offset Drift Dependence of Hall Cells with their Designed Geometry
Autorzy:: Paun, M. A.
Sallese, J. M.
Kayal, M.
Powiązania:: https://bibliotekanauki.pl/articles/226531.pdf
Data publikacji:: 2013
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: hall effect sensor
individual and residual offset drift
temperature coefficient
Opis:: In this paper, the performance of CMOS Hall Effect Sensors with four different geometries has been experimentally studied. Using a characteristic measurement system, the cells residual offset and its temperature behavior were determined. The offset, offset drift and sensitivity are quantities that were computed to determine the sensors performance. The temperature coefficient of specific parameters such as individual, residua offset and resistance has been also investigated. Therefore the optimum cell to fit the best in the performance specifications was identified. The variety of tested shapes ensures a good analysis on how the sensors performance changes with geometry.
Źródło:: International Journal of Electronics and Telecommunications; 2013, 59, 2; 169-175
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: SPICE simulation of passive N-type guard rings in smart power ICs
Autorzy:: Buccella, P.
Stefanucci, C.
Sallese, J.-M.
Kayal, M.
Powiązania:: https://bibliotekanauki.pl/articles/397726.pdf
Data publikacji:: 2015
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: substrate modeling
noise coupling
power parasitic modelling
modelowanie substratów
sprzężenie zakłóceń
zasilanie pasożytnicze
Opis:: When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a SPICE-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our approach consists in integrating a new substrate model in SPICE to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.
Źródło:: International Journal of Microelectronics and Computer Science; 2015, 6, 2; 64-68
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 4.

Tytuł:: Spice simulation of substrate potential shift in HVCMOS technologies
Autorzy:: Stefanucci, C.
Buccella, P.
Kayal, M.
Sallese, J.-M.
Powiązania:: https://bibliotekanauki.pl/articles/397879.pdf
Data publikacji:: 2015
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: Smart Power ICs
HVCMOS modeling
vertical bipolar transistor
substrate potential shift
Smart Power
modelowanie HVCMOS
pionowy tranzystor bipolarny
Opis:: High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.
Źródło:: International Journal of Microelectronics and Computer Science; 2015, 6, 4; 142-147
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 5.

Tytuł:: Measurement and performance evaluation of a silicon on insulator pixel matrix
Autorzy:: Ntavelis, D.
Harik, L.
Sallese, J.-M.
Kayal, M.
Hatzopoulos, A.
Powiązania:: https://bibliotekanauki.pl/articles/397821.pdf
Data publikacji:: 2010
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: technika SOI tranzystora polowego MOS
czujnik obrazu
pompować ładunek
pierwsza kolejność delta-sigma
SOI MOSFET
image sensors
charge pumping
first order delta-sigma
Opis:: A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.
Źródło:: International Journal of Microelectronics and Computer Science; 2010, 1, 3; 299-304
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

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