Autor: Jakubowski, L. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: An impact of frequency on capacitances of partially-depleted SOI MOSFETs
Autorzy:: Tomaszewski, D.
Łukasik, L.
Zaręba, A.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/309325.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
small-signal models
non-quasi-static analysis
admittances
Opis:: A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 67-71
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: An impact of physical phenomena on admittances of partially-depleted SOI MOSFETs
Autorzy:: Tomaszewski, D.
Łukasiak, L.
Gibki, J.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/308410.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
floating body
avalanche ionization
recombination
displacement current
admittance
Opis:: An influence of the selected physical phenomena: impact ionization in silicon and time variation of internal electric field distribution in partially-depleted (PD) SOI MOSFETs on several C-V characteristics of these devices is presented. The role of avalanche multiplication in the so-called "pinch-off" region is discussed in a more detailed way. The analysis is done using a numerical solver of drift-diffusion equations in silicon devices and using an analytical model of the PD SOI MOSFETs. The calculations results exhibit the significance of proper modelling of the phenomena in the floating body area of these devices.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 57-60
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: A model of partially-depleted SOI MOSFETs in the subthreshold range
Autorzy:: Tomaszewski, D.
Łukasiak, L.
Jakubowski, A.
Domański, K.
Powiązania:: https://bibliotekanauki.pl/articles/308425.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
subthreshold range
floating body
transconductance
Opis:: A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in current continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion-based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the "pinch-off" region and avalanche multiplication triggered by these carriers. Characteristics of the presented model are shown and briefly discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 61-64
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Standardization of the compact model coding: non-fully depleted SOI MOSFET example
Autorzy:: Grabiński, W.
Tomaszewski, D.
Lemaitre, L.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/308862.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: Verilog-AMS
compact model coding
SOI MOSFET
Opis:: The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 135-141
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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