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Wyszukujesz frazę "Jakubowski, L." wg kryterium: Autor

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    Wyświetlanie 1-13 z 13
    Tytuł:
    History of Semiconductors
    Autorzy:
    Łukasiak, L.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308134.pdf
    Data publikacji:
    2010
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    band theory
    laser
    Moore's law
    semiconductors
    transistor
    Opis:
    The history of semiconductors is presented beginning with the first documented observation of a semiconductor effect (Faraday), through the development of the first devices (point-contact rectifiers and transistors, early field-effect transistors) and the theory of semiconductors up to the contemporary devices (SOI and multigate devices).
    Źródło:
    Journal of Telecommunications and Information Technology; 2010, 1; 3-9
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Modeling of the inverse base width modulation effect in HBT transistor with graded SiGe base
    Autorzy:
    Zaręba, A.
    Łukasiak, L.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308625.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    heterojunction bipolar transistor
    SiGe
    base width modulation
    Opis:
    A model of the position of the edge of emitter-base junction in the base and collector current pre-exponential ideality factor in HBT transistor with a SiGe base is presented. The model is valid for transistors with nonuniform profiles of doping and Ge content. The importance of taking into account the dependence of the effective density of states in SiGe on local Ge content and that of electron diffusion coefficient in SiGe on drift field for modeling accuracy is studied.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 3; 88-92
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Modeling SiGe-base HBT using APSYS 2000 - a 2D simulator
    Autorzy:
    Linkowski, A.
    Łukasiak, L.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308023.pdf
    Data publikacji:
    2004
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    base transit time
    cut-off frequency
    HBT
    SiGe-base
    Opis:
    The paper is devoted to optimization of SiGe-base HBT with respect to operation speed by means of numerical simulation. The influence of design parameters on f(T) is studied.
    Źródło:
    Journal of Telecommunications and Information Technology; 2004, 1; 36-38
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Silicon microelectronics: where we have come from and where we are heading
    Autorzy:
    Łukasiak, L.
    Jakubowski, A.
    Pióro, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/308029.pdf
    Data publikacji:
    2004
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    MOSFET
    scaling
    SiGe
    SOI
    Opis:
    The paper briefly presents the history of microelectronics and the limitations of its further progress, as well as possible solutions. The discussion includes the consequences of the reduction of gate-stack capacitance and difficulties associated with supply-voltage scaling, minimization of parasitic resistance, increased channel doping and small size. Novel device architectures (e.g. SON, double-gate transistor) and the advantages of silicon-germanium are considered, too.
    Źródło:
    Journal of Telecommunications and Information Technology; 2004, 1; 7-14
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Comparison of 4H-SiC and 6H-SiC MOSFET I-V characteristics simulated with Silvaco Atlas and Crosslight Apsys
    Autorzy:
    Stęszewski, J.
    Jakubowski, A.
    Korwin-Pawlowski, M. L.
    Powiązania:
    https://bibliotekanauki.pl/articles/308627.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    silicon carbide
    SiC MOSFET
    4H-SiC
    6H-SiC
    Crosslight Apsys
    Silvaco Atlas
    Opis:
    A set of physical models describing silicon carbide with fitting parameters is proposed. The theoretical I-V output and transfer characteristics and parameters of MOS transistors were calculated using Silvaco Atlas and Crosslight Apsys semiconductor device simulation environments.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 3; 93-95
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Arbitrary waveform generator for charge-pumping
    Autorzy:
    Iwanowicz, M.
    Pióro, Z.
    Łukasiak, L.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308629.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    arbitrary waveform generator,
    calibration
    charge-pumping
    digital synthesis
    noise
    Opis:
    The paper presents a new signal generator for charge-pumping. Modular structure of the generator is discussed with special emphasis on signal-generation module consisting of five independent signal channels. Digital signal synthesis is chosen to minimize inaccuracies. Noise analysis is performed to demonstrate the validity of the design of signal channel. Calibration procedure is also discussed.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 3; 78-83
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An impact of frequency on capacitances of partially-depleted SOI MOSFETs
    Autorzy:
    Tomaszewski, D.
    Łukasik, L.
    Zaręba, A.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/309325.pdf
    Data publikacji:
    2000
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    SOI MOSFET
    small-signal models
    non-quasi-static analysis
    admittances
    Opis:
    A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed.
    Źródło:
    Journal of Telecommunications and Information Technology; 2000, 3-4; 67-71
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An impact of physical phenomena on admittances of partially-depleted SOI MOSFETs
    Autorzy:
    Tomaszewski, D.
    Łukasiak, L.
    Gibki, J.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308410.pdf
    Data publikacji:
    2001
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    SOI MOSFET
    floating body
    avalanche ionization
    recombination
    displacement current
    admittance
    Opis:
    An influence of the selected physical phenomena: impact ionization in silicon and time variation of internal electric field distribution in partially-depleted (PD) SOI MOSFETs on several C-V characteristics of these devices is presented. The role of avalanche multiplication in the so-called "pinch-off" region is discussed in a more detailed way. The analysis is done using a numerical solver of drift-diffusion equations in silicon devices and using an analytical model of the PD SOI MOSFETs. The calculations results exhibit the significance of proper modelling of the phenomena in the floating body area of these devices.
    Źródło:
    Journal of Telecommunications and Information Technology; 2001, 1; 57-60
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A model of partially-depleted SOI MOSFETs in the subthreshold range
    Autorzy:
    Tomaszewski, D.
    Łukasiak, L.
    Jakubowski, A.
    Domański, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/308425.pdf
    Data publikacji:
    2001
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    SOI MOSFET
    subthreshold range
    floating body
    transconductance
    Opis:
    A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in current continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion-based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the "pinch-off" region and avalanche multiplication triggered by these carriers. Characteristics of the presented model are shown and briefly discussed.
    Źródło:
    Journal of Telecommunications and Information Technology; 2001, 1; 61-64
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Standardization of the compact model coding: non-fully depleted SOI MOSFET example
    Autorzy:
    Grabiński, W.
    Tomaszewski, D.
    Lemaitre, L.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308862.pdf
    Data publikacji:
    2005
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    Verilog-AMS
    compact model coding
    SOI MOSFET
    Opis:
    The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
    Źródło:
    Journal of Telecommunications and Information Technology; 2005, 1; 135-141
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Challenges in ultrathin oxide layers formation
    Autorzy:
    Beck, R.B.
    Jakubowski, A.
    Łukasiak, L.
    Korwin-Pawłowski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/307646.pdf
    Data publikacji:
    2001
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    silicon technology
    oxidation
    PECVD
    RTO
    gate oxide
    ultrathin
    layers
    Opis:
    In near future silicon technology cannot do without ultrathin oxides, as it becomes clear from the "Roadmap'2000". Formation, however, of such layers, creates a lot of technical and technological problems. The aim of this paper is to present the technological methods, that potentially can be used for formation of ultrathin oxide layers for next generations ICs. The methods are briefly described and their pros and cons are discussed.
    Źródło:
    Journal of Telecommunications and Information Technology; 2001, 1; 27-34
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis of the Dispersion of Electrical Parameters and Characteristics of FinFET Devices
    Autorzy:
    Malinowski, A.
    Tomaszewski, D.
    Łukasiak, L.
    Jakubowski, A.
    Sekine, M.
    Hori, M.
    Korwin-Pawlowski, M. L.
    Powiązania:
    https://bibliotekanauki.pl/articles/308253.pdf
    Data publikacji:
    2009
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    FinFET
    line edge roughness
    parameter variability
    plasma etching
    technology computer aided design (TCAD)
    Opis:
    Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD tools. A series of plasma etching steps has been simulated for different process conditions in order to evaluate the influence of plasma pressure, composition and powering on the FinFET topography. Next, the most important geometric parameters of the FinFETs have been varied and the electrical characteristics have been calculated in order to evaluate the sensitivity of the FinFET electrical parameters on possible FinFET structure variability.
    Źródło:
    Journal of Telecommunications and Information Technology; 2009, 4; 45-50
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Characterization of SOI fabrication process using gated-diode measurements and TEM studies
    Autorzy:
    Gibki, J.
    Kątcki, J.
    Ratajczak, J.
    Łukasik, L.
    Jakubowski, A.
    Tomaszewski, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/309219.pdf
    Data publikacji:
    2000
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    microelectronics
    SOI technology
    characterization
    Opis:
    SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods.
    Źródło:
    Journal of Telecommunications and Information Technology; 2000, 3-4; 81-83
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-13 z 13

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