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    Wyświetlanie 1-13 z 13
    Tytuł:
    Dissolution Behavior of Metal Impurities and Improvement of Reclaimed Semiconductor Wafer Cleaning by Addition of Chelating Agent
    Autorzy:
    Ryu, Keunhyuk
    Kim, Myungsuk
    Roh, Jaeseok
    Lee, Kun-Jae
    Powiązania:
    https://bibliotekanauki.pl/articles/2049175.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    reclaimed silicon wafer
    wafer cleaning
    metal impurity
    metal complex
    chelating agent
    Opis:
    As a wafer cleaning process, RCA (Radio Corporation of America) cleaning is mainly used. However, RCA cleaning has problems such as instability of bath life, re-adsorption of impurities and high-temperature cleaning. Herein, we tried to improve the purity of silicon wafers by using a chelating agent (oxalic acid) to solve these problems. Compounds produced by the reaction between the cleaning solution and each metal powder were identified by referring to the pourbaix diagram. All metals exhibited a particle size distribution of 10 μm or more before reaction, but a particle size distribution of 500 nm or less after reaction. In addition, it was confirmed that the metals before and after the reaction showed different absorbances. As a result of elemental analysis on the surface of the reclaimed silicon wafer cleaned through such a cleaning solution, it was confirmed that no secondary phase was detected other than Si.
    Źródło:
    Archives of Metallurgy and Materials; 2021, 66, 4; 977-981
    1733-3490
    Pojawia się w:
    Archives of Metallurgy and Materials
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multi-technique characterisation of InAs-on-GaAs wafers with circular defect pattern
    Autorzy:
    Boguski, Jacek
    Wróbel, Jarosław
    Złotnik, Sebastian
    Budner, Bogusław
    Liszewska, Malwina
    Kubiszyn, Łukasz
    Michałowski, Paweł P.
    Ciura, Łukasz
    Moszczyński, Paweł
    Odrzywolski, Sebastian
    Jankiewicz, Bartłomiej
    Wróbel, Jerzy
    Powiązania:
    https://bibliotekanauki.pl/articles/2204219.pdf
    Data publikacji:
    2023
    Wydawca:
    Polska Akademia Nauk. Stowarzyszenie Elektryków Polskich
    Tematy:
    wafer homogeneity
    wafer defect pattern
    surface roughness
    indium arsenide
    beryllium doping
    Opis:
    The article presents the results of diameter mapping for circular-symmetric disturbance of homogeneity of epitaxially grown InAs (100) layers on GaAs substrates. The set of acceptors (beryllium) doped InAs epilayers was studied in order to evaluate the impact of Be doping on the 2-inch InAs-on-GaAs wafers quality. During the initial identification of size and shape of the circular pattern, non-destructive optical techniques were used, showing a 100% difference in average roughness between the wafer centre and its outer part. On the other hand, no volumetric (bulk) differences are detectable using Raman spectroscopy and highresolution X-ray diffraction. The correlation between Be doping level and circular defect pattern surface area has been found.
    Źródło:
    Opto-Electronics Review; 2023, 31, Special Issue; art. no. e144564
    1230-3402
    Pojawia się w:
    Opto-Electronics Review
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Freeze-dried elderberry and chokeberry as natural colorants for gluten-free wafer sheets
    Autorzy:
    Różyło, R.
    Wójcik, M.
    Dziki, D.
    Biernacka, B.
    Cacak-Pietrzak, G.
    Gawłowski, S.
    Zdybel, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/2082495.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Instytut Agrofizyki PAN
    Tematy:
    natural colorant
    elderberry
    chokeberry
    gluten-
    free
    wafer
    Opis:
    Freeze-dried elderberry and chokeberry were proposed as natural colorants for gluten-free wafers. In addition to colour, other physical and sensorial properties of wafer sheets were also evaluated. The elderberry powder was significantly darker (L* equal 37.61) than the chokeberry powder (L* equal 41.01), and it was characterized by a considerably lower a* value (4.21 in comparison with 12.32). These powdered fruits were added in the range from 0 to 5 %. A new indicator of wafer batter delamination was developed, which can also be proposed for other liquids. Significant and favourable changes were noted in the colour of both batter and wafers, with an increased content of fruits from 1 to 5%. Gluten-free wafers with a 5% addition of fruits were characterized by L*, a*, b* values, respectively, equalling 35.73, 6.05 and 3.24 for elderberry, and 39.74, 7.15 and 5.05 for chokeberry. Wafers with a 5% addition of chokeberry and elderberry, in comparison to control wafers, had significantly higher contents of minerals, including iron, potassium, calcium, magnesium and sodium. The freeze-dried elderberry powder, as compared to the chokeberry powder, was found to significantly increase the content of these minerals. In addition, the total flavonoids content was higher in the wafers containing elderberry. Freeze-dried chokeberry and elderberry can be proposed as natural colorants and valuable functional components for wafers.
    Źródło:
    International Agrophysics; 2019, 33, 2; 217-225
    0236-8722
    Pojawia się w:
    International Agrophysics
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Ocena przydatnosci maki pszenzytniej do produkcji wafli
    Autorzy:
    Sucharzewska, D
    Nebesny, E.
    Powiązania:
    https://bibliotekanauki.pl/articles/826089.pdf
    Data publikacji:
    2000
    Wydawca:
    Polskie Towarzystwo Technologów Żywności
    Tematy:
    wypiek
    listki waflowe
    wafle
    wartosc wypiekowa
    receptury
    maka pszenzytnia
    baking
    wafer sheet
    wafer
    baking value
    recipe
    triticale flour
    Opis:
    Określono przydatność mąki pszenżytniej do wypieku listków waflowych. W oparciu o recepturą tradycyjną na wafle z udziałem mąki pszennej badano możliwość całkowitego zastąpienia mąki pszennej mąką pszenżytnią oraz mieszanką z mąką pszenżytnią. Badano wyróżniki mąki charakteryzujące jej przydatność technologiczną do wypieku wafli. Stwierdzono, że w wyniku niewielkiej modyfikacji receptury możliwe jest uzyskanie dobrych jakościowo listków waflowych z samej mąki pszenżytniej. Znacznie lepsze jakościowo wafle uzyskuje się wzmacniając ich strukturę dodatkiem mąki pszennej. Ustalono, że najkorzystniejszy udział mąki pszenżytniej w odniesieniu do mąki pszennej wynosił 65%. Przy ustalaniu proporcji mąki pszenżytniej do pszennej należy brać pod uwagę szczególnie ilość i jakość glutenu mieszanki. Nie stwierdzono natomiast niekorzystnego wpływu podwyższonej aktywności amylolitycznej mąki pszennno-żytniej na jakość listków waflowych.
    The quality of Triticale flour was assessed for the purpose of wafer baking. Basing on the traditional recipe of wafers, with the wheat flour, the possibility of substituting wheat flour completely with Triticale flour, as well as with a mixture of wheat flour and Triticale flour, was tested. The factors of flour, characterising its technology for the purpose of wafer baking, were tested. It was found that as a result of a slight modification of the recipe, it is possible to obtain good quality wafers out of Triticale flour alone. A considerable better quality is to be obtained by fortifying their structure with an additive of wheat flour. It was determined that the most advantageous fraction of Triticale flour in relation to wheat flour amounted to 65%. In the course of determining the proportion of Triticale flour in relation to wheat flour, particularly the quantity and quality of the gluten of the mixture is to be taken into consideration. On the other hand, no unfavourable influence of an increased amylolytic activity of starch contained in Triticale flour, on the quality of wafer flakes, was found.
    Źródło:
    Żywność Nauka Technologia Jakość; 2000, 07, 1; 82-91
    1425-6959
    Pojawia się w:
    Żywność Nauka Technologia Jakość
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pairs of successes in Bernoulli trials and a new n-estimator for the binomial distribution
    Autorzy:
    Kühne, Wolfgang
    Neumann, Peter
    Stoyan, Dietrich
    Stoyan, Helmut
    Powiązania:
    https://bibliotekanauki.pl/articles/1340510.pdf
    Data publikacji:
    1994
    Wydawca:
    Polska Akademia Nauk. Instytut Matematyczny PAN
    Tematy:
    n-estimator
    simulation
    silicon wafer
    Markov chain
    binomial distribution
    Opis:
    The problem of estimating the number, n, of trials, given a sequence of k independent success counts obtained by replicating the n-trial experiment is reconsidered in this paper. In contrast to existing methods it is assumed here that more information than usual is available: not only the numbers of successes are given but also the number of pairs of consecutive successes. This assumption is realistic in a class of problems of spatial statistics. There typically k = 1, in which case the classical estimators cannot be used. The quality of the new estimator is analysed and, for k > 1, compared with that of a classical n-estimator. The theoretical basis for this is the distribution of the number of success pairs in Bernoulli trials, which can be determined by an elementary Markov chain argument.
    Źródło:
    Applicationes Mathematicae; 1993-1995, 22, 3; 331-337
    1233-7234
    Pojawia się w:
    Applicationes Mathematicae
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Detection of Monocrystalline Silicon Wafer Defects Using Deep Transfer Learning
    Autorzy:
    Ganum, Adriana
    Iskandar, D. N. F. Awang
    Chin, Lim Phei
    Fauzi, Ahmad Hadinata
    Powiązania:
    https://bibliotekanauki.pl/articles/2058502.pdf
    Data publikacji:
    2022
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    automated optical inspection
    machine learning
    neural network
    wafer imperfection identification
    Opis:
    Defect detection is an important step in industrial production of monocrystalline silicon. Through the study of deep learning, this work proposes a framework for classifying monocrystalline silicon wafer defects using deep transfer learning (DTL). An existing pre-trained deep learning model was used as the starting point for building a new model. We studied the use of DTL and the potential adaptation of Mo bileNetV2 that was pre-trained using ImageNet for extracting monocrystalline silicon wafer defect features. This has led to speeding up the training process and to improving performance of the DTL-MobileNetV2 model in detecting and classifying six types of monocrystalline silicon wafer defects (crack, double contrast, hole, microcrack, saw-mark and stain). The process of training the DTL-MobileNetV2 model was optimized by relying on the dense block layer and global average pooling (GAP) method which had accelerated the convergence rate and improved generalization of the classification network. The monocrystalline silicon wafer defect classification technique relying on the DTL-MobileNetV2 model achieved the accuracy rate of 98.99% when evaluated against the testing set. This shows that DTL is an effective way of detecting different types of defects in monocrystalline silicon wafers, thus being suitable for minimizing misclassification and maximizing the overall production capacities.
    Źródło:
    Journal of Telecommunications and Information Technology; 2022, 1; 34--42
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Reduction of defects in the lapping process of the silicon wafer manufacturing: the Six Sigma application
    Autorzy:
    Sharma, Mithun
    Sahni, Sanjeev P.
    Sharma, Shilpi
    Powiązania:
    https://bibliotekanauki.pl/articles/125540.pdf
    Data publikacji:
    2019
    Wydawca:
    Politechnika Białostocka. Oficyna Wydawnicza Politechniki Białostockiej
    Tematy:
    Six Sigma
    quality
    silicon wafer
    lapping
    quality control
    total thickness variation
    wafer manufacturing
    jakość
    płytka krzemowa
    docieranie
    kontrola jakości
    całkowita zmiana grubości
    produkcja płytek
    Opis:
    Aiming to reduce flatness (Total Thickness Variation, TTV) defects in the lapping process of the silicon wafer manufacturing, it is crucial to understand and eliminate the root cause(s). Financial losses resulting from TTV defects make the lapping process unsustainable. DMAIC (Define, Measure, Analyse, Improve and Control), which is a Six Sigma methodology, was implemented to improve the quality of the silicon wafer manufacturing process. The study design and the choice of procedures were contingent on customer requirements and customised to ensure maximum satisfaction; which is the underlying principle of the rigorous, statistical technique of Six Sigma. Previously unknown causes of high TTV reject rates were identified, and a massive reduction in the TTV reject rate was achieved (from 4.43% to 0.02%). Also, the lapping process capability (Ppk) increased to 3.87 (beyond the required standard of 1.67), suggesting sustainable long-term stability. Control procedures were also effectively implemented using the techniques of poka yoke and control charts. This paper explores the utility of Six Sigma, a quality management technique, to improve the quality of a process used in the semiconductor industry. The application of the Six Sigma methodology in the current project provides an example of the root cause investigation methodology that can be adopted for similar processes or industries. Some of the statistical tools and techniques were used for the first time in this project, thereby providing new analysis and quality improvement platform for the future. The article offers a deeper understanding of the factors that impact on the silicon wafer flatness in the lapping process. It also highlights the benefits of using a structured problem-solving methodology like Six Sigma.
    Źródło:
    Engineering Management in Production and Services; 2019, 11, 2; 87-105
    2543-6597
    2543-912X
    Pojawia się w:
    Engineering Management in Production and Services
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A probabilistic approach for approximation of optical and opto-electronic properties of an opto-semiconductor wafer under consideration of measuring inaccuracy and model uncertainty
    Autorzy:
    Stroka, Stefan M.
    Heumann, Christian
    Suhrke, Fabian
    Meindl, Kathrin
    Powiązania:
    https://bibliotekanauki.pl/articles/2204192.pdf
    Data publikacji:
    2023
    Wydawca:
    Polska Akademia Nauk. Stowarzyszenie Elektryków Polskich
    Tematy:
    Gaussian process regression
    machine learning
    uncertainty quantification
    photoluminescence
    opto-semiconductor wafer measuring
    Opis:
    This paper presents a probabilistic machine learning approach to approximate wavelength values for unmeasured positions on an opto-semiconductor wafer after epitaxy. Insufficient information about optical and opto-electronic properties may lead to undetected specification violations and, consequently, to yield loss or may cause product quality issues. Collection of information is restricted because physical measuring points are expensive and in practice samples are only drawn from 120 specific positions. The purpose of the study is to reduce the risk of uncertainties caused by sampling and measuring inaccuracy and provide reliable approximations. Therefore, a Gaussian process regression is proposed which can determine a point estimation considering measuring inaccuracy and further quantify estimation uncertainty. For evaluation, the proposed method is compared with radial basis function interpolation using wavelength measurement data of 6-inch InGaN wafers. Approximations of these models are evaluated with the root mean square error. Gaussian process regression with radial basis function kernel reaches a root mean square error of 0.814 nm averaged over all wafers. A slight improvement to 0.798 nm could be achieved by using a more complex kernel combination. However, this also leads to a seven times higher computational time. The method further provides probabilistic intervals based on means and dispersions for approximated positions.
    Źródło:
    Opto-Electronics Review; 2023, 31, 2; art. no. e145863
    1230-3402
    Pojawia się w:
    Opto-Electronics Review
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis of errors in on-wafer measurements due to multimode propagation in CB-CPW
    Autorzy:
    Lewandowski, A.
    Wiatr, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/307779.pdf
    Data publikacji:
    2005
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    on-wafer measurements
    multimode propagation
    error analysis
    conductor-backed coplanar waveguide (CB-CPW)
    microstrip-like mode
    numerical electromagnetic analysis
    on-wafer probe
    calibration
    de-embedding
    monolithic microwave integrated circuit (MMIC)
    Opis:
    We study for the first time errors in on-wafer scattering parameter measurements caused by the parasitic microstrip-like mode propagation in conductor-backed coplanar waveguide (CB-CPW). We determine upper bound for these errors for typical CPW devices such as a matched load, an open circuit, and a transmission line section. To this end, we develop an electromagnetic-simulations-based multimode three-port model for the transition between an air-coplanar probe and the CB-CPW. Subsequently, we apply this model to examine errors in the device S parameters de-embedded from measurements affected by the parasitic MSL mode. Our analysis demonstrates that the multimode propagation in CB-CPW may significantly deteriorate the S-parameters measured on wafer.
    Źródło:
    Journal of Telecommunications and Information Technology; 2005, 2; 16-22
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method
    Autorzy:
    Liu, H.
    Dong, Z.
    Kang, R.
    Zhou, P.
    Gao, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/220380.pdf
    Data publikacji:
    2015
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    flatness measurement
    large and thin silicon wafer
    GID
    three-point-support method
    initial stress
    Opis:
    Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID) of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM) including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.
    Źródło:
    Metrology and Measurement Systems; 2015, 22, 4; 531-546
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model
    Autorzy:
    Mattausch, H. J.
    Yumisaki, A.
    Sadachika, N.
    Kaya, A.
    Johguchi, K.
    Koide, T.
    Miura-Mattausch, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/308251.pdf
    Data publikacji:
    2009
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    compact model
    fabrication inaccuracy
    field-effect transistor
    macroscopic
    microscopic
    potential at channel surface
    silicon
    within wafer
    Opis:
    An analysis of the measured macroscopic withinwafer variations for threshold voltage (Vth) and on-current (Ion) over several technology generations (180 nm, 100 nm and 65 nm) is reported. It is verified that the dominant microscopic variations of the MOSFET device can be extracted quantitatively from these macroscopic variation data by applying the surface-potential compact model Hiroshima University STARC IGFET model 2 (HiSIM2), which is presently brought into industrial application. Only a small number of microscopic parameters, representing substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier-mobility degradation due to gate-interface roughness (MUESR1) and channel-length variation during the gate formation (XLD) are found sufficient to quantitatively reproduce the measured macroscopic within-wafer variations of Vth and Ion for all channel length Lg and all technology generations. Quantitative improvements from 180 nm to 65 nm are confirmed to be quite large for MUESR1 (about 70%) and Lmin(XLD) (55%) variations, related to the gate-oxide interface and the gate-stack structuring, respectively. On the other hand, doping-related technology advances, which are reflected by the variation magnitudes of NSUBC (30%) and NSUBP (25%), are found to be considerably smaller. Furthermore, specific combinations of extreme microscopic parameter-variation values are able to represent the boundaries of macroscopic fabrication inaccuracies for Vth and Ion. These combinations are found to remain identical, not only for all Lg of a given technology node, but also for all investigated technologies with minimum Lg of 180 nm, 100 nm and 65 nm.
    Źródło:
    Journal of Telecommunications and Information Technology; 2009, 4; 37-44
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Metal-titanium oxide / quantum dot porous silicon / silicon-metal solar cell
    Autorzy:
    Abd, Ahmad Naji
    Mishjil, Khudheir A.
    Abdulsada, Ali Hamid
    Habubi, N. F.
    Powiązania:
    https://bibliotekanauki.pl/articles/1177996.pdf
    Data publikacji:
    2018
    Wydawca:
    Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
    Tematy:
    AFM
    FTIR
    TiO2
    X-Ray diffraction
    XRD
    electrochemical etching p-type silicon wafer
    nanocrystalline porous silicon
    Opis:
    In this paper, the nanocrystalline porous silicon (PSi) films are prepared by electrochemical etching of p-type silicon wafer with current density 7 mA/cm2 and etching times on the formation nano-sized pore array with a dimension of around different etching time. The films were characterized by the measurement of XRD, FTIR spectroscopy and atomic force microscopy properties (AFM). We have estimated crystallites size from X-Ray diffraction about nanoscale for porous silicon and Atomic Force microscopy confirms the nanometric size Chemical fictionalization during the electrochemical etching show on the surface chemical composition of PS. The etching possesses inhomogeneous microstructures that contain a-Si clusters (Si3–Si–H) dispersed in amorphous silica matrix. From the FTIR analyses showed that the Si dangling bonds of the as-prepared PS layer have large amount of Hydrogen to form weak Si–H bonds. The atomic force microscopy investigation shows the rough silicon surface, with increasing etching process (current density and etching time) porous structure nucleates which leads to an increase in the depth and width (diameter) of surface pits. Consequently, the surface roughness also increase.
    Źródło:
    World Scientific News; 2018, 96; 134-148
    2392-2192
    Pojawia się w:
    World Scientific News
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Correction of the electric resistivity distribution of Si wafers using selective neutron transmutation doping (SNTD) in MARIA nuclear research reactor
    Autorzy:
    Tarchalski, M.
    Kordyasz, A. J.
    Pytel, K.
    Dorosz, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/146646.pdf
    Data publikacji:
    2012
    Wydawca:
    Instytut Chemii i Techniki Jądrowej
    Tematy:
    silicon wafer
    thermal neutron doping
    silicon resistivity homogeneity
    silicon resistivity heterogeneity
    neutron transmutation doping (NTD)
    selective neutron transmutation doping (SNTD)
    MARIA nuclear research reactor
    Opis:
    The result of the electric resistivity distribution modification in silicon wafers, by means of selective neutron transmutation doping (SNTD) method in the MARIA nuclear research reactor at Świerk/Otwock (Poland) is presented. Silicon wafer doping system has been fully designed for the MARIA reactor, where irradiation took place. The silicon wafer resistivity distribution after SNTD has been measured by the capacity voltage (C-V) method. In this article we show first results of this correction technique. The result of the present investigation is that the planar resolution of the correction process is about 4 mm. It is the full width at half maximum (FWHM) of the resistivity distribution produced by thermal neutrons irradiation of Si wafer through a 3 mm hole in the Cd-mask.
    Źródło:
    Nukleonika; 2012, 57, 3; 363-367
    0029-5922
    1508-5791
    Pojawia się w:
    Nukleonika
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-13 z 13

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