Temat: substrate noise - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Interconnections coupling through substrate for frequencies up to 100 GHz
Autorzy:: Gerakis, V
Hatzopoulos, A.
Powiązania:: https://bibliotekanauki.pl/articles/397752.pdf
Data publikacji:: 2014
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: substrate noise
interconnect coupling
substrate doping
S-parameters
Z-parameters
zakłócenia podłożowe
domieszkowanie substratu
parametry rozproszenia
parametry impedancji
Opis:: This work presents a study on the substrate noise coupling between two interconnects. A highly, a lightly and a uniformly doped substrate, approximating most modern technologies, are described. The three different doping profiles are simulated for various interconnect distances and different metal layers assuming a 65 nm bulk CMOS technology. A proper data analysis methodology is presented, including z and s parameters extraction and de-embedding procedure.
Źródło:: International Journal of Microelectronics and Computer Science; 2014, 5, 4; 144-148
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Automated substrate resistance extraction in nanoscale VLSI by exploiting a geometry-based analytical model
Autorzy:: Bontzios, Y. I.
Dimopoulos, M. G.
Hatzopoulos, A. A.
Powiązania:: https://bibliotekanauki.pl/articles/398110.pdf
Data publikacji:: 2011
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: szum podłożowy
układ scalony
modelowanie geometryczne
pochodzenie oporu
modelowanie oporu
zasilanie pasożytnicze
substrate noise
integrated circuits
geometric modeling
resistance extraction
resistance modeling
parasitics
Opis:: In this work, a new automated method for determining the substrate resistance is presented. It exploits a geometric formulation of the current streamlines between coupled structures and builds an analytical model for the substrate resistance. Both simulation and measurement data are utilized in order to show the validity of the proposed scheme. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance while the average error falls within 5%.
Źródło:: International Journal of Microelectronics and Computer Science; 2011, 2, 3; 81-87
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: SPICE simulation of passive N-type guard rings in smart power ICs
Autorzy:: Buccella, P.
Stefanucci, C.
Sallese, J.-M.
Kayal, M.
Powiązania:: https://bibliotekanauki.pl/articles/397726.pdf
Data publikacji:: 2015
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: substrate modeling
noise coupling
power parasitic modelling
modelowanie substratów
sprzężenie zakłóceń
zasilanie pasożytnicze
Opis:: When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a SPICE-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our approach consists in integrating a new substrate model in SPICE to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.
Źródło:: International Journal of Microelectronics and Computer Science; 2015, 6, 2; 64-68
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

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