Temat: splitting area - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Large halocline variations in the Northern Baltic Proper and associated meso- and basin-scale processes
Autorzy:: Elken, J.
Malkki, P.
Alenius, P.
Stipa, T.
Powiązania:: https://bibliotekanauki.pl/articles/47628.pdf
Data publikacji:: 2006
Wydawca:: Polska Akademia Nauk. Instytut Oceanologii PAN
Tematy:: Sopot
current
splitting area
Finland Gulf
saline water
conference
Baltic Sea
halocline
Opis:: The Northern Baltic Proper is a splitting area of the Baltic Sea saline water route towards the two terminal basins – the Gulf of Finland and the Western Gotland Basin. Large halocline variations (vertical isopycnal displacements of more than 20 m, intra-halocline current speeds above 20 cm s−1) appear during and following SW wind events, which rapidly increase the water storage in the Gulf of Finland and reverse the standard estuarine transport, causing an outflow in the lower layers. In the channel of variable topography, basin-scale barotropic flow pulses are converted into baroclinic mesoscale motions such as jet currents, sub-surface eddies and lowfrequency waves. The associated dynamics is analysed by the results from a special mesoscale experiment, routine observations and numerical modelling.
Źródło:: Oceanologia; 2006, 48, S
0078-3234
Pojawia się w:: Oceanologia
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Finite-state State Machines Minimization by Using of Values of Input Variables at State Assignment
Autorzy:: Salauyou, V.
Ostapczuk, M.
Powiązania:: https://bibliotekanauki.pl/articles/114436.pdf
Data publikacji:: 2017
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:: finite state machine (FSM)
programmable gate array (FPGA)
state assignment
area minimization
state splitting
Opis:: In this paper, we propose a method of FSM synthesis on field programmable gate arrays (FPGAs) when input variables are used for state assignment. For this purpose we offer a combined structural model of class A and class E FSMs. This paper also describes in detail algorithms for synthesis a class AE FSM which consists of splitting of internal states for performance of necessary conditions for synthesis of the class E FSM and state assignment of the class AE FSM. It is shown that the proposed method reduces the area for all families of FPGAs by a factor of 1.19…1.39 on average and by a factor of 3.00 for certain families.
Źródło:: Measurement Automation Monitoring; 2017, 63, 5; 195-197
2450-2855
Pojawia się w:: Measurement Automation Monitoring
Dostawca treści:: Biblioteka Nauki

Artykuł

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