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Wyszukujesz frazę "silicon nanowire" wg kryterium: Temat


Wyświetlanie 1-3 z 3
Tytuł:
Black Silicon Obtained in Two-Step Short Wet Etching as a Texture for Silicon Solar Cells - Surface Microstructure and Optical Properties Studies
Autorzy:
Kulesza-Matlak, G.
Gawlińska, K.
Starowicz, Z.
Sypień, A.
Drabczyk, K.
Drabczyk, B.
Lipiński, M.
Zięba, P.
Powiązania:
https://bibliotekanauki.pl/articles/352242.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
black silicon
low temperature texturization
silicon nanowire
solar cells
multicrystalline silicon
Opis:
In this study a two-step short wet etching was implemented for the black silicon formation. The proposed structure consists of two steps. The first step: wet acidic etched pits-like morphology with a quite new solution of lowering the texturization temperature and second step: wires structure obtained by a metal assisted etching (MAE). The temperature of the process was chosen due to surface development control and surface defects limitation during texturing process. This allowed to maintain better minority carrier lifetime compared to etching in ambient temperature. On the top of the acidic texture the wires were formed with optimized height of 350 nm. The effective reflectance of presented black silicon structure in the wavelength range of 300-1100 nm was equal to 3.65%.
Źródło:
Archives of Metallurgy and Materials; 2018, 63, 2; 1009-1017
1733-3490
Pojawia się w:
Archives of Metallurgy and Materials
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Single-electron transport characteristics in quantum dot arrays due to ionized dopants
Autorzy:
Moraru, D.
Ligowski, M.
Tarido, J. C.
Miki, S.
Nakamura, R.
Yokoi, K.
Mizuno, T.
Tabe, M.
Powiązania:
https://bibliotekanauki.pl/articles/384277.pdf
Data publikacji:
2009
Wydawca:
Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
Tematy:
single dopant
silicon nanowire
single-electron transport
single-electron transfer
Opis:
Single charge manipulation for useful electronic functionalities has become an exciting and fast-paced direction of research in recent years. In structures with dimensions below about 100 nm, the physics governing the device operation turn out to be strikingly different than in the case of larger devices. The presence of even a single charge may completely suppress current flow due to the basic electronelectron repulsion (so called Coulomb blockade effect) [1]. It is even more exciting to control this effect at the level of single-electron/single-atom interaction. The atomic entity can be one donor present in silicon lattice with a Coulombic potential well. In principle, it can accommodate basically a single electron. We study the electrical behavior of nanoscale-channel silicon-on-insulator field-effect transistors (SOI-FETs) that contain a discrete arrangement of donors. The donors can be utilized as "stepping stones" for the transfer of single charges. This ability opens the doors to a rich world of applications based on the simple interplay of single charges and single atoms, while still utilizing mostly conventional and well established fabrication techniques. In this work, we distinguish the effects of single-electron transport mediated by one or few dopants only. Furthermore, we show how the single-electron/single-donor interaction can be tuned by using the external biases. We demonstrate then by simulation and experiment the feasibility of single-electron/bit transfer operation (single-electron turnstile).
Źródło:
Journal of Automation Mobile Robotics and Intelligent Systems; 2009, 3, 4; 52-54
1897-8649
2080-2145
Pojawia się w:
Journal of Automation Mobile Robotics and Intelligent Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Challenges for 10 nm MOSFET process integration
Autorzy:
Östling, M.
Malm, B. G.
Haartman, M.
Hallstedt, J.
Zhang, Z.
Hellström, P. E.
Zhang, S.
Powiązania:
https://bibliotekanauki.pl/articles/309004.pdf
Data publikacji:
2007
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
sstrained silicon
silicon-germanium
silicon-on-insulator (SOI)
high-k dielectrics
hafnium oxide
nanowire
low frequency noise
mobility
metal gate
Opis:
An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.
Źródło:
Journal of Telecommunications and Information Technology; 2007, 2; 25-32
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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