- Tytuł:
- Challenges in scaling of CMOS devices towards 65 nm node
- Autorzy:
-
Jurczak, M.
Veloso, A.
Rooyackers, R.
Augendre, E.
Mertens, S.
Rotschild, A.
Scaekers, M.
Lindsay, R.
Lauwers, A.
Henson, K.
Severi, S.
Pollentier, I.
Keersgieter de, A. - Powiązania:
- https://bibliotekanauki.pl/articles/308984.pdf
- Data publikacji:
- 2005
- Wydawca:
- Instytut Łączności - Państwowy Instytut Badawczy
- Tematy:
-
CMOS devices
gate dielectrics
shallow junctions
silicide
gate stack
lithography
gate patterning
silicon recess
device integration - Opis:
- The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electrical device specifications especially leakage current and the circuit power dissipation.
- Źródło:
-
Journal of Telecommunications and Information Technology; 2005, 1; 3-6
1509-4553
1899-8852 - Pojawia się w:
- Journal of Telecommunications and Information Technology
- Dostawca treści:
- Biblioteka Nauki
Artykuł