- Tytuł:
- Improving LUT count of FPGA-based sequential blocks
- Autorzy:
-
Barkalov, Alexander
Titarenko, Larysa
Mazurkiewicz, Małgorzata
Krzywicki, Kazimierz - Powiązania:
- https://bibliotekanauki.pl/articles/2173598.pdf
- Data publikacji:
- 2021
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
FPGA
LUT
Mealy FSM
synthesis
structural decomposition
product terms
partition
automat Mealy'ego
synteza
rozkład strukturalny
warunki produktu
przegroda - Opis:
- Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
- Źródło:
-
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; art. no. e136728
0239-7528 - Pojawia się w:
- Bulletin of the Polish Academy of Sciences. Technical Sciences
- Dostawca treści:
- Biblioteka Nauki
Artykuł