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    Wyświetlanie 1-7 z 7
    Tytuł:
    Effective residue-to-binary converter with the Chinese Remainder Theorem
    Efektywna konwersja liczb z systemu resztowego do systemu wagowego z uzyciem chińskiego twierdzenia o resztach
    Autorzy:
    Ulman, Z.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/152042.pdf
    Data publikacji:
    2003
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    cyfrowe przetwarzanie sygnałów
    szybka arytmetyka komputerowa
    resztowy system liczbowy
    digital signal processing
    fast computer arithmetic
    residue number system
    residue-to-binary converter
    Opis:
    The residue-to-binary conversion is the key operation in all digital signal processing applications that use the Residue Number System (RNS). In this work a new conversion technique based on the Chinese Remainder Theorem (CRT) for 5- and 6-bit moduli is proposed. It is especially suited for the realization with the use of binary arithmetic. the specific property of the realization with the use of binary arithmetic. The specific property of the technique is a way of calculation of the excess factor r in the CRT formula that makes possible, under certain conditions, the reduction of processed numbers from the range [0,nM) to [0,2M) where "M" is the product of moduli. This is done by replacing the calculation of "r" by the computation of the result of division of the sum of projections by a power of 2 close to M. Such approach allows for very effective hardware realization of the converter. Only small ROM`s and standard binary adders are required. Moreover, the pipelining on the Full-Adder (FA) level possible.
    Konwersja liczb z systemu resztowego do systemu binarnego jest podstawową operacją we wszystkich układach cyfrowego przetwarzania sygnałów, które wykorzystują system resztowy. W niniejszej pracy zaproponowano nowa metodę konwersji opartą o chinskie twierdzenie o resztach dla modułów 5- i 6-bitowych. Specyficzną cechą nowej metody jest sposób obliczania tzw. współczynnika pomiaru "r" w formule chińskiego twierdzenia o resztach, co umożliwia pod pewnymi warunkami, redukcję przetwarzanych liczb z zakresu [0,nM) do [0,2M). Jest to realizowane poprzez zastąpienie obliczania "r" obliczaniem rB, gdzie M jest potęgą liczby 2 bliska M. Takie podejście pozwala na bardzo efektywną sprzętową realizację konwertora. Konieczne są tylko małe pamięci typu ROM i standardowe sumatory binarne. ponadto możliwa jest realizacja potokowa z częstotliwością ograniczoną opóźnieniem sumatora 1-bitowego.
    Źródło:
    Pomiary Automatyka Kontrola; 2003, R. 49, nr 12, 12; 34-38
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Hierarchical residue number systems with small moduli and simple converters
    Autorzy:
    Tomczak, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/907828.pdf
    Data publikacji:
    2011
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    arytmetyka cyfrowa
    układ cyfrowy
    resztowy system liczbowy
    digital arithmetic
    digital circuits
    residue number system
    VLSI
    Opis:
    In this paper, a new class of Hierarchical Residue Number Systems (HRNSs) is proposed, where the numbers are represented as a set of residues modulo factors of 2k š 1 and modulo 2k. The converters between the proposed HRNS and the positional binary number system can be built as 2-level structures using efficient circuits designed for the RNS (2k - 1, 2k, 2k +1). This approach allows using many small moduli in arithmetic channels without large conversion overhead. The advantages resulting from the use of the proposed HRNS depend on the possibility of factorisation of moduli [...].
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2011, 21, 1; 173-192
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
    Autorzy:
    Smyk, R.
    Ulman, Z.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/376378.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    pipelining
    residue number system
    RNS
    residue arithmetic
    Opis:
    In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 117-126
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Residue number system (RNS)
    Autorzy:
    Sharoun, A. O.
    Powiązania:
    https://bibliotekanauki.pl/articles/376029.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    RNS
    residue arithmetic
    Opis:
    In the residue number system, a set of moduli which are independent of each other is given. An integer is represented by the residue of each modulus and the arithmetic operations are based on the residues individually. The arithmetic operations based on residue number system can be performed on various moduli independently to avoid the carry in addition, subtraction and multiplication, which is usually time consuming. However, the comparison and division are more complicated and the fraction number computation is immatured. Due to this, a residue number system is not yet popular in general-purpose computers, though it is extremely useful for digital-signal-processing applications. This thesis deals with the design, simulation and microcontroller implementation of some (residue number system based) building blocks for applications in the field of digital signal processing. The building blocks which have been studied are binary to residue converter, residue to binary converter, residue adder and residue multiplier.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 265-270
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaling of numbers in residue arithmetic with the flexible selection of scaling factor
    Autorzy:
    Ulman, Z.
    Czyżak, M.
    Smyk, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/376813.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    scaling technique
    scaling factor
    residue arithmetic
    Residue Number System
    RNS
    Mixed-Radix System
    MRS
    Opis:
    A scaling technique of numbers in residue arithmetic with the flexible selection of the scaling factor is presented. The required scaling factor can be selected from the set of moduli products of the Residue Number System (RNS) base. By permutation of moduli of the number system base it is possible to create many auxiliary Mixed-Radix Systems (MRS). They serve as the intermediate systems in the scaling process. All MRS's are associated with the given RNS with respect to the base, but they have different sets of weights. For the scaling factor value resulting from the requirements of the given signal processing algorithm, the suitable MRS can be chosen that allows to obtain the scaling result in most simple manner.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 175-179
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multifunctional unit for reverse conversion and sign detection based on five-moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }
    Autorzy:
    Mojahed, Mohsen
    Molahosseini, Amir Sabbagh
    Zarandi, Azadeh Alsadat Emrani
    Powiązania:
    https://bibliotekanauki.pl/articles/2097893.pdf
    Data publikacji:
    2021
    Wydawca:
    Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
    Tematy:
    computer arithmetic
    residue number system
    reverse converter
    Opis:
    A high dynamic range moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3} has recently been introduced as an arithmetically balanced five-modull set for the residue number system (RNS). In order to utilize this moduli set in applications handling signed numbers, two important components are needed: a sign detector, and a signed reverse converter. However, having both of these components results in high-hardware requirements, which makes RNS impractical. This paper overcomes this problem by designing a unified unit that can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors’ knowledge, this is the first attempt to design a sign detector for a moduli set that includes a {2 n 3} moduli. In order to achieve a hardwareamenable design, we first improved the performance of the previous unsigned reverse converter for this moduli set. Then, we extracted a sign-detection method from the structure of the reverse converter. Finally, we made an unsigned reverse converter-to-sign converter through the use of the extracted sign signal from the reverse converter. The experimental results show that the proposed reverse convertor and sign detector result in improvements of 31% and 28% in area and delay, respectively, as compared to the previous unsigned reverse convertor with sign output using a comparator.
    Źródło:
    Computer Science; 2021, 22 (1); 101-121
    1508-2806
    2300-7036
    Pojawia się w:
    Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    SIGN detection and signed integer comparison for three-moduli SET {2n ±1, 2n+k}
    Autorzy:
    Torabi, Zeinab
    Timarchi, Somayeh
    Powiązania:
    https://bibliotekanauki.pl/articles/2097970.pdf
    Data publikacji:
    2021
    Wydawca:
    Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
    Tematy:
    computer arithmetic
    residue number system
    signed integer comparison
    dynamic range partitioning
    Opis:
    Comparison, division, and sign detection are considered to be complicated op erations in a residue number system (RNS). A straightforward solution is to convert RNS numbers into binary formats and then perform complicated op erations using conventional binary operators. If efficient circuits are provided for comparison, division, and sign detection, the application of RNS can be extended to those cases that include these operations. For RNS comparison in three-moduli set τ = {2 n−1, 2 n+k , 2 n+1},(0 ≤ k ≤ n), we have found only one hardware realization. In this paper, an efficient RNS comparator is proposed for moduli set τ , which employs a sign-detection method and operates more efficiently than its counterparts. The proposed sign detector and comparator utilize dynamic range partitioning (DRP), which has been recently presented for unsigned RNS comparison. The delay and cost of the proposed comparator are lower than the previous works, which makes it appropriate for RNS applications with limited delay and cost.
    Źródło:
    Computer Science; 2021, 22 (3); 387-401
    1508-2806
    2300-7036
    Pojawia się w:
    Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-7 z 7

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