Temat: pipelined implementation - Katalog OPAC zbiorów

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Tytuł:: Pipelined architectures for the frequency domain linear equalizer
Autorzy:: Glentis, G. O.
Georgoulakis, K.
Powiązania:: https://bibliotekanauki.pl/articles/908377.pdf
Data publikacji:: 2006
Wydawca:: Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:: dziedzina częstotliwości
przetwarzanie potokowe
urządzenie wyrównawcze
adaptive equalization
frequency domain LMS
pipelined implementation
Opis:: In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simulation results are presented that illustrate the performance of the effect of the time delay introduced into the adaptation algorithm. The proposed architectures for efficient pipelining of the FD LMS linear equalization algorithm are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.
Źródło:: International Journal of Applied Mathematics and Computer Science; 2006, 16, 4; 525-535
1641-876X
2083-8492
Pojawia się w:: International Journal of Applied Mathematics and Computer Science
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Pipeline processing in low-density parity-check codes hardware decoder
Autorzy:: Sułek, W.
Powiązania:: https://bibliotekanauki.pl/articles/202316.pdf
Data publikacji:: 2011
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: channel coding
LDPC codes
iterative decoding
decoder implementation
pipelined processing
Opis:: Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation – and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2011, 59, 2; 149-155
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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