- Tytuł:
- Analysis and Design of a First - Order Delta-Sigma Modulator based on Ultra Incomplete Settling and Considering Non-ideal Effects
- Autorzy:
-
Nowacki, B.
Paulino, N.
Goes, J. - Powiązania:
- https://bibliotekanauki.pl/articles/397918.pdf
- Data publikacji:
- 2012
- Wydawca:
- Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
- Tematy:
-
modulator Delta-Sigma
integrator bierny
konwersja analogowo-cyfrowa
konwersja A/D
filtr S.C.
delta-sigma modulator
passive integrator
analog-to-digital conversion
A/D conversion
passive SC filter - Opis:
- One of the main building blocks of a Delta-Sigma modulator (ΔΣ?) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣcircuit based on the implementation of passive switched-capacitor (SC) integrator using ultra incomplete settling. The behavior of a 1st order ΔΣ? is fully analyzed and explained, as well as its non-ideal effects, which become more significant for higher clock frequencies. This work compares performance of ΔΣM clocked with Fclk=100 MHz and Fclk=300 MHz. Electrical simulations show that the ΔΣM (Fclk=300 MHz) achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 67.5 dB, a peak signal-to-noise ratio (SNR) of 69.7 dB for a signal with a bandwidth (BW) of 400 kHz, while dissipating only 232μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 165 fJ/conv.-step (simulated).
- Źródło:
-
International Journal of Microelectronics and Computer Science; 2012, 3, 4; 125-131
2080-8755
2353-9607 - Pojawia się w:
- International Journal of Microelectronics and Computer Science
- Dostawca treści:
- Biblioteka Nauki
Artykuł