- Tytuł:
- Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization
- Autorzy:
-
Domański, Krzysztof
Głuszko, Grzegorz
Sierakowski, Andrzej
Tomaszewski, Daniel
Szmigiel, Dariusz - Powiązania:
- https://bibliotekanauki.pl/articles/397763.pdf
- Data publikacji:
- 2018
- Wydawca:
- Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
- Tematy:
-
VeSTIC
VeSFET
logic cell
logic integrated circuit
ring oscillator
parasitic element
oscillation frequency
compact modeling
komórka logiczna
logiczny układ scalony
generator pierścieniowy
częstotliwość oscylacji
kompaktowe modelowanie - Opis:
- A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.
- Źródło:
-
International Journal of Microelectronics and Computer Science; 2018, 9, 3; 123-132
2080-8755
2353-9607 - Pojawia się w:
- International Journal of Microelectronics and Computer Science
- Dostawca treści:
- Biblioteka Nauki
Artykuł