Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

Wyszukujesz frazę "parametric circuits" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Time-Domain Synthesis of Linear Circuits With Periodically Variable Parameters
Autorzy:
Siwczyński, M.
Powiązania:
https://bibliotekanauki.pl/articles/911223.pdf
Data publikacji:
2000
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
układ parametryczny
synteza
optymalizacja
parametric circuits
synthesis
optimisation
Opis:
A novel synthesis method of linear electric networks with periodically variable parameters is presented. These types of networks can be implemented as resistance-parametric, (conductance-capacitance)-parametric or (resistance- inductance)- parametric multiports. The time-varying parameters are determined so as to extremize some specific optimisation criteria. Consequently, the synthesis task has a unique solution. The starting point of the solution method is the original theorem proved in the paper, which deals with the minimum-energy networks.
Źródło:
International Journal of Applied Mathematics and Computer Science; 2000, 10, 3; 623-637
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Soft Fault Clustering in Analog Electronic Circuits with the Use of Self Organizing Neural Network
Autorzy:
Grzechca, D.
Powiązania:
https://bibliotekanauki.pl/articles/220571.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
fault detection
parametric faults
analogue electronic circuits
self-organizing neural network
Opis:
The paper presents a methodology for parametric fault clustering in analog electronic circuits with the use of a self-organizing artificial neural network. The method proposed here allows fast and efficient circuit diagnosis on the basis of time and/or frequency response which may lead to higher production yield. A self-organizing map (SOM) has been applied in order to cluster all circuit states into possible separate groups. So, it works as a feature selector and classifier. SOM can be fed by raw data (data comes from the time or frequency response) or some pre-processing is done at first. The author proposes conversion of a circuit response with the use of e.g. gradient and differentiation. The main goal of the SOM is to distribute all single faults on a two-dimensional map without state overlapping. The method is aimed for the development stage because the tolerances of elements are not taken into account, however single but parametric faults are considered. Efficiency analyses of fault clustering have been made on several examples e.g. a Sallen-Key BPF and an ECG amplifier. Testing procedure is performed in time and frequency domains for the Sallen-Key BPF with limited number of test points i.e. it is assumed that only input and output pins are available. A similar procedure has been applied to a real ECG amplifier in the frequency domain. Results prove a high efficiency in acceptable time which makes the method very convenient (easy and quick) as a first test in the development stage.
Źródło:
Metrology and Measurement Systems; 2011, 18, 4; 555-568
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

    Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies