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Tytuł:
On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor
Autorzy:
Smyk, R.
Czyżak, M.
Powiązania:
https://bibliotekanauki.pl/articles/97551.pdf
Data publikacji:
2014
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
fast Fourier transform
residue number system
modified quadratic residue number system
pipelined FFT processor
Opis:
Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be scaled, i.e. divided by a certain constant. The number range of the processed signal increases due to transformation of coefficients of the FFT algorithm to integers and summation and multiplication within the butterfly. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two residue scalers are needed.
Źródło:
Computer Applications in Electrical Engineering; 2014, 12; 588-596
1508-4248
Pojawia się w:
Computer Applications in Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor
Autorzy:
Smyk, R.
Czyżak, M.
Powiązania:
https://bibliotekanauki.pl/articles/377692.pdf
Data publikacji:
2014
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
fast Fourier transform
residue number system
modified quadratic residue number system
FFT pipelined processor
Opis:
Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled, i.e. divided by a certain constant. The dynamic range of the processed signal increases due to the summation within the butterfly and the transformation of coefficients of the FFT algorithm to integers. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two scalers are needed.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 145-150
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Residue number system (RNS)
Autorzy:
Sharoun, A. O.
Powiązania:
https://bibliotekanauki.pl/articles/376029.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
residue number system
RNS
residue arithmetic
Opis:
In the residue number system, a set of moduli which are independent of each other is given. An integer is represented by the residue of each modulus and the arithmetic operations are based on the residues individually. The arithmetic operations based on residue number system can be performed on various moduli independently to avoid the carry in addition, subtraction and multiplication, which is usually time consuming. However, the comparison and division are more complicated and the fraction number computation is immatured. Due to this, a residue number system is not yet popular in general-purpose computers, though it is extremely useful for digital-signal-processing applications. This thesis deals with the design, simulation and microcontroller implementation of some (residue number system based) building blocks for applications in the field of digital signal processing. The building blocks which have been studied are binary to residue converter, residue to binary converter, residue adder and residue multiplier.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 265-270
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
Autorzy:
Smyk, R.
Ulman, Z.
Czyżak, M.
Powiązania:
https://bibliotekanauki.pl/articles/376378.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
pipelining
residue number system
RNS
residue arithmetic
Opis:
In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 117-126
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multifunctional unit for reverse conversion and sign detection based on five-moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }
Autorzy:
Mojahed, Mohsen
Molahosseini, Amir Sabbagh
Zarandi, Azadeh Alsadat Emrani
Powiązania:
https://bibliotekanauki.pl/articles/2097893.pdf
Data publikacji:
2021
Wydawca:
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
Tematy:
computer arithmetic
residue number system
reverse converter
Opis:
A high dynamic range moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3} has recently been introduced as an arithmetically balanced five-modull set for the residue number system (RNS). In order to utilize this moduli set in applications handling signed numbers, two important components are needed: a sign detector, and a signed reverse converter. However, having both of these components results in high-hardware requirements, which makes RNS impractical. This paper overcomes this problem by designing a unified unit that can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors’ knowledge, this is the first attempt to design a sign detector for a moduli set that includes a {2 n 3} moduli. In order to achieve a hardwareamenable design, we first improved the performance of the previous unsigned reverse converter for this moduli set. Then, we extracted a sign-detection method from the structure of the reverse converter. Finally, we made an unsigned reverse converter-to-sign converter through the use of the extracted sign signal from the reverse converter. The experimental results show that the proposed reverse convertor and sign detector result in improvements of 31% and 28% in area and delay, respectively, as compared to the previous unsigned reverse convertor with sign output using a comparator.
Źródło:
Computer Science; 2021, 22 (1); 101-121
1508-2806
2300-7036
Pojawia się w:
Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Propriétés topologiques et combinatoires des échelles de numération
Autorzy:
Barat, Guy
Downarowicz, Tomasz
Iwanik, Anzelm
Liardet, Pierre
Powiązania:
https://bibliotekanauki.pl/articles/965769.pdf
Data publikacji:
2000
Wydawca:
Polska Akademia Nauk. Instytut Matematyczny PAN
Tematy:
dynamical system
addingi machine
odometer
rooted tree
number system
Opis:
Topological and combinatorial properties of dynamical systems called odometers and arising from number systems are investigated. First, a topological classification is obtained. Then a rooted tree describing the carries in the addition of 1 is introduced and extensively studied. It yields a description of points of discontinuity and a notion of low scale, which is helpful in producing examples of what the dynamics of an odometer can look like. Density of the orbits is also discussed.
Źródło:
Colloquium Mathematicum; 2000, 84/85, 2; 285-306
0010-1354
Pojawia się w:
Colloquium Mathematicum
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pipelined scaling of signed residue numbers with the mixed-radix conversion in the programmable gate array
Autorzy:
Czyżak, M.
Smyk, R.
Ulman, Z.
Powiązania:
https://bibliotekanauki.pl/articles/377373.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
scaling technique
Mixed-Radix System
MRS
Residue Number System
pipelining
Opis:
In this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System(MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign is detected on the basis of the value of the most significant coefficient of the MRS representation. For negative numbers their residues are adequately corrected. The basic blocks of the scaler are realized in the form of the modified two-operand modulo adders with included additional multiply and modulo reduction operations. The pipelined realization of the scaler in the Xilinx environment is shown and analyzed with respect to hardware amount and maximum pipelining frequency. The design is based on the LUTs(26x 1) that simulate small RAMs serving as the main component for the look-up realization.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 89-99
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pipelined division of signed numbers with the use of residue arithmetic in FPGA
Autorzy:
Czyżak, M.
Smyk, R.
Ulman, Z.
Powiązania:
https://bibliotekanauki.pl/articles/97191.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
residue number system
division
multiplicative division algorithm
scaling
FPGA
Opis:
An architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length of the look-up table address, a reciprocal computation algorithm based on segmentation of the divisor into two segments is used. The signed approximate reciprocal, transformed to the residue representation, is stored in look-up tables division and multiplied by the dividend in the residue form. The obtained quotient is scaled. The pipelined realization of the divider in the FPGA environment is also shown.
Źródło:
Computer Applications in Electrical Engineering; 2013, 11; 455-464
1508-4248
Pojawia się w:
Computer Applications in Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Scaled residue reverse converter for signed numbers with low cost moduli base
Autorzy:
Czyżak, Maciej
Smyk, Robert
Powiązania:
https://bibliotekanauki.pl/articles/376503.pdf
Data publikacji:
2019
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
residue number system
residue reverse conversion
scaling
low-cost moduli
Opis:
The paper presents a realization of the scaled residue reverse converter for the low cost moduli base {2n -1,2n ,2n+1} . The moduli of this type allow for the memoryless reverse conversion using the Chinese Remainder Theorem because the orthogonal projections can be obtained by shifts and additions. Moreover, the modulo reduction of the sum of projections and sign detection algorithms are shown. Also the converter architecture is presented.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2019, 98; 101-114
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection
Autorzy:
Smyk, R.
Czyżak, M.
Ulman, Z.
Powiązania:
https://bibliotekanauki.pl/articles/97226.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
residue number system
RNS
scaling
scaling algorithms
mixed-radix system
MRS
FPGA
Opis:
A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign of the residue number is detected by using the most significant digit of the MRS representation. Basic blocks of the scaler are realized in the form of modified two-operand modulo adders with included additional multiply and modulo reduction operations. An exemplary pipelined realization of the scaler in the Xilinx FPGA environment is shown. The design is based on Look-Up Tables (LUT)(2,sup>6 x 1) that simulate small RAMs which serve as main components for the look-up realization. Also a method is shown that allows for flexible selection of scaling factors from a set of moduli products of the RNS base. This is made by forming auxiliary MRSs by permutation of moduli of the base. All formed MRSs are associated with the given RNS with respect to the base but each MRS has different set of weights. Thus for the required scaling factor, the suitable MRS can be chosen that provides for the scaling error smaller than 1.
Źródło:
Computer Applications in Electrical Engineering; 2013, 11; 465-477
1508-4248
Pojawia się w:
Computer Applications in Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-10 z 62

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