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Wyświetlanie 1-2 z 2
Tytuł:
Area equivalent WKB Compact modeling approach for tunneling probability in Hetero-Junction TFETs including ambipolar behaviour
Autorzy:
Horst, Fabian
Farokhnejad, Atieh
Darbandy, Ghader
Iñíguez, Benjamín
Kloes, Alexander
Powiązania:
https://bibliotekanauki.pl/articles/397787.pdf
Data publikacji:
2018
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
TFET
tunneling probability
WKB approximation
heterojunction
compact modeling
closed-form
double-gate
DG
ambipolarity
modelowanie kompaktowe
dwubiegunowość
Opis:
This paper introduces an innovative modeling approach for calculating the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs). The field of application is the usage in TFET compact models. Looking at a tunneling process in TFETs, carriers try to tunnel through an energy barrier which is defined by the device band diagram. The tunneling energy barrier is approximated by an approach which assumes an area equivalent (AE) triangular shaped energy profile. The simplified energy triangle is suitable to be used in the Wentzel-Kramers-Brillouin (WKB) approximation. Referring to the area instead of the electric field at individual points is shown to be a more robust approach in terms of numerical stability. The derived AE approach is implemented in an existing compact model for double-gate (DG) TFETs. In order to verify and show the numerical stability of this approach, modeling results are compared to TCAD Sentaurus simulation data for various sets of device parameters, whereby the simulations include both ON- and AMBIPOLAR-state of the TFET. In addition to the various device dimensions, the source material is also changed to demonstrate the feasibility of simulating hetero-junctions. Comparing the modeling approach with TCAD data shows a good match. Apart the limitations demonstrated and discussed in this paper, the main advantage of the AE approach is the simplicity and a better fit to TCAD data in comparison to the quasi-2D WKB approach.
Źródło:
International Journal of Microelectronics and Computer Science; 2018, 9, 2; 47-59
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization
Autorzy:
Domański, Krzysztof
Głuszko, Grzegorz
Sierakowski, Andrzej
Tomaszewski, Daniel
Szmigiel, Dariusz
Powiązania:
https://bibliotekanauki.pl/articles/397763.pdf
Data publikacji:
2018
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
VeSTIC
VeSFET
logic cell
logic integrated circuit
ring oscillator
parasitic element
oscillation frequency
compact modeling
komórka logiczna
logiczny układ scalony
generator pierścieniowy
częstotliwość oscylacji
kompaktowe modelowanie
Opis:
A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.
Źródło:
International Journal of Microelectronics and Computer Science; 2018, 9, 3; 123-132
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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