Temat: loop unrolling - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Research on the maritime communication cryptographic chip’s compiler optimization
Autorzy:: Li, S.
Dai, Z. B.
Powiązania:: https://bibliotekanauki.pl/articles/259239.pdf
Data publikacji:: 2017
Wydawca:: Politechnika Gdańska. Wydział Inżynierii Mechanicznej i Okrętownictwa
Tematy:: maritime communication encryption system
cryptographic SOC
compiler frontend
loop unrolling
Opis:: In the process of ocean development, the technology for maritime communication system is a hot research field, of which information security is vital for the normal operation of the whole system, and that is also one of the difficulties in the research of maritime communication system. In this paper, a kind of maritime communication cryptographic SOC(system on chip) is introduced, and its compiler framework is put forward through analysis of working mode and problems faced by compiler front end. Then, a loop unrolling factor calculating algorithm based on queue theory, named UFBOQ (unrolling factor based on queue), is proposed to make parallel optimization in the compiler frontend with consideration of the instruction memory capacity limit. Finally, the scalar replacement method is used to optimize unrolled code to solve the memory access latency on the parallel computing efficiency, for continuous data storage characteristics of cryptographic algorithm. The UFBOQ algorithm and scalar replacement prove effective and appropriate, of which the effect achieves the linear speedup.
Źródło:: Polish Maritime Research; 2017, S 2; 50-65
1233-2585
Pojawia się w:: Polish Maritime Research
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2069086.pdf
Data publikacji:: 2015
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: block cipher
hash function
hardware implementation
loop unrolling
pipelining
FPGA
Opis:: The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
Źródło:: Journal of Polish Safety and Reliability Association; 2015, 6, 2; 117--124
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2068736.pdf
Data publikacji:: 2018
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: hardware implementation
loop unrolling
pipelining
AES
BLAKE
KECCAK
SHA-3
Opis:: Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
Źródło:: Journal of Polish Safety and Reliability Association; 2018, 9, 3; 75--84
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Implementing SHA-3 candidate BLAKE algorithm in Field Programmable Gate Arrays
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2069234.pdf
Data publikacji:: 2016
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: BLAKE algorithm
FPGA
hash function
implementation efficiency
loop unrolling
pipelining
Opis:: BLAKE is a cryptographic hash function proposed as a candidate in SHA-3 contest where he successfully qualified to the final round with other 4 candidates. Although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and great performance especially in software realizations. For these advantages BLAKE is commonly selected to be a hash function of choice in many contemporary IT systems in applications like digital signatures or message authentication. The purpose of this paper is to evaluate how the algorithm is suitable to be implemented in hardware using low-cost Field Programmable Gate Array (FPGA) devices, particularly to test how efficiently its complex internal transformations can be realized with FPGA resources when overall size of the implementation grows substantially with multiple rounds of the cipher running in parallel in hardware and capacity of the configurable array is used up to its limits. The study was made using the set of 7 different architectures with different loop unrolling factors and with optional application of pipelining, with each architecture being implemented in two popular families of FPGA devices from Xilinx. Investigation of the internal characteristic of the implementations generated by the tools helped in analysis how the fundamental mechanism of loop unrolling with or without pipelining works in case of this particular cipher.
Źródło:: Journal of Polish Safety and Reliability Association; 2016, 7, 1; 193--200
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Memory resources in hardware implementations of BLAKE and BLAKE2 hash algorithms
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2068924.pdf
Data publikacji:: 2017
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: BLAKE hash algorithm
implementation efficiency
memory
loop unrolling
resource utilization
Opis:: In contemporary computer systems security issues are very important for both safety and reliability reasons thus application of appropriate cryptographic methods is a necessity in system design and maintenance. This paper deals with one such method – BLAKE hash function – and investigates its implementation in hardware. The algorithm was a candidate proposed for the SHA-3 contest and, although it was not selected in the final round as the winner, it was very well received for its cryptographic strength and performance, being still used as a hash method of choice in contemporary IT systems. In this paper we discuss a specific modification in hardware realizations of the function which eliminates need for involved data paths distributing message bits among the round units by using auxiliary memory modules for repetitive storage of the message inside each round instance. The idea was implemented in realizations of both BLAKE and BLAKE2 versions of the algorithm in four different organizations: the standard iterative one and three high-speed loop-unrolled architectures with 2, 4 and 5 rounds instantiated in hardware. Together with standard (without RAM) implementations this produced a total of 16 test cases: after implementation in a popular Spartan-3 device from Xilinx their parameters allowed for exhaustive evaluation of the proposed modification. The results reveal that the modification outstandingly enhances size of all the tested architectures: on average, occupation of the FPGA array is reduced at least by half while the improvements in speed, although not so spectacular, are also visible. Additional analyses indicate that the method can also increase overall efficiency of routing, helps in implementation of the loop-unrolled architectures and strengthens optimizations introduced by the BLAKE2 version of the algorithm.
Źródło:: Journal of Polish Safety and Reliability Association; 2017, 8, 1; 119--128
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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