Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

Wyszukujesz frazę "logic design" wg kryterium: Temat


Tytuł:
Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate
Autorzy:
Węgrzyn, M.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/226665.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic design
state machines
logic devices
FPGA
VHDL
Opis:
The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; onehot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 357-362
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Probes for fault localization in computer networks
Autorzy:
Traczyk, W.
Powiązania:
https://bibliotekanauki.pl/articles/308948.pdf
Data publikacji:
2004
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
fault localization
probes
computer networks
partitions
logic design
Opis:
Fault localization is a process of isolating faults responsible for the observable malfunctioning of the managed system. This paper reviews some existing approaches of this process and improves one of described techniques - the probing. Probes are test transactions that can be actively selected and sent through the network. Suggested innovations include: mixed (passive and active) probing, partitioning used for probe selection, logical detection of probing results, and adaptive, sequential probing.
Źródło:
Journal of Telecommunications and Information Technology; 2004, 3; 23-27
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
www-Based Boolean Function Minimization
Autorzy:
Tomaszewski, S. P.
Celik, I. U.
Antoniou, G. E.
Powiązania:
https://bibliotekanauki.pl/articles/908086.pdf
Data publikacji:
2003
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
informatyka
digital logic
logic design
Boolean function
Boolean minimization
Quine-McCluskey metod
Opis:
In this paper a Boolean minimization algorithm is considered and implemented as an applet in Java. The application is based on the Quine-McCluskey simplification technique with some modifications. The given application can be accessed on line since it is posted on the World Wide Web (WWW), with up to four variables, at the URL http://www.csam.montclair.edu/~antoniou/bs. After extensive testing, the performance of the algorithm has been found to be excellent. The proposed application is a useful aid for students and professors in the fields of electrical and computer engineering and computer science as well as a valuable tool for digital designers.
Źródło:
International Journal of Applied Mathematics and Computer Science; 2003, 13, 4; 577-583
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Structured Mapping of Petri Net States and Events for FPGA Implementations
Autorzy:
Tkacz, J.
Adamski, M.
Powiązania:
https://bibliotekanauki.pl/articles/227222.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
configurable logic controllers
interpreted Petri net state space
local and global state encoding
hyperpgraph
logic design
Gentzen sequents
Petri net coloring
FPGA
VHDL
Opis:
The paper presents a new method of structured encoding of global internal states and events in Reconfigurable Logic Controllers, which are directly mapped into Field Programmable Gate Arrays (FPGA). Modular, concurrently decomposed, colored state machine is chosen as a intermediate model, before the mapping of Petri net into an array structure of dedicated but very flexible and reliable digital system. The initial textual specification in formal Gentzen logic serves both as a design description for a rapid prototyping, as well as formal model, suitable for detailed computer-based reasoning about optimized and synthesized logic controller, implemented in configurable hardware. Only the selected linear subset from general, universal propositional Gentzen Logic is necessary to deduce several properties of the net, such as relations of nonconcurrency among structurally ordered macroplaces. The goal of this paper is to present the design methodology for modeling and synthesis of discrete controllers using related Petri net theory, rule-based theory (mathematical logic), and VHDL.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 331-339
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
CP approach to design of steady-state flow of repetitive manufacturing processes in SME
Autorzy:
Wójcik, R.
Bocewicz, G.
Powiązania:
https://bibliotekanauki.pl/articles/118159.pdf
Data publikacji:
2005
Wydawca:
Polskie Towarzystwo Promocji Wiedzy
Tematy:
production planning
waiting-free schedules design
constraint logic programming
Opis:
Concurrent execution of work orders in the small and medium size enterprises (SME) imposes a necessity to consider many control problems concerning systems of repetitive concurrent manufacturing processes using common resources in mutual exclusion. In many cases a production system with a given structure of the processes resource requests can be seen as composed of subsystems with n cyclic processes sharing one resource. For given sets of possible values of the processes operation execution times a problem of finding schedules guaranteeing that no process waits for access to the common resources is considered. In particular for the assigned times of the operations execution a subproblem of finding all possible starting times of work orders execution for which waiting-free schedules exist has been formulated as a constraint programming (CP) problem. The starting times derived can be used as an alternative starting times of work orders execution in case of their possible delays. A state space of the problem’s solutions has been reduced using constraints based on the necessary and sufficient conditions for existence of a waiting-free n-process steady-state schedule. An illustrative example of Mozart-based software application to the solution of constraint logic programming problem considered has been presented.
Źródło:
Applied Computer Science; 2005, 1, 1; 201-218
1895-3735
Pojawia się w:
Applied Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Coupled fuzzy logic and experimental design application for simulation of a coal classifier in an industrial environment
Autorzy:
Khoshdast, Hamid
Soflaeian, Ali
Shojaei, Vahideh
Powiązania:
https://bibliotekanauki.pl/articles/109838.pdf
Data publikacji:
2019
Wydawca:
Politechnika Wrocławska. Oficyna Wydawnicza Politechniki Wrocławskiej
Tematy:
combined modeling
fuzzy logic
experimental design
coal classifier
industry
Opis:
Design of experiments (DOE) is an effective method providing useful information about the interaction of operating variables and the way the total system works by using statistical analyses. However, its industrial application is limited because it is almost difficult to maintain variables in DOE matrix at desired constant levels in industrial environment. Thus, this paper aims to present a new mixed modeling method which is a combination of fuzzy logic and design of experiments methods to overcome such practical limitations. The method first uses a fuzzy model which is trained by practical data gathered from industry to predict DOE response corresponding to each run in DOE matrix. Then, a statistical parametric model is constructed for the prediction of process response to any change of operating parameters under real industrial conditions. The proposed mixed method was successfully validated by using data obtained from a coal hydraulic classifier at Zarand Coal Washing Plant (Kerman, Iran). The method also seems to be a promising tool for modeling all devices and processes in real industrial environment and allows researchers to benefit from all the advantages of experimental design and fuzzy logic methods simultaneously.
Źródło:
Physicochemical Problems of Mineral Processing; 2019, 55, 2; 504-515
1643-1049
2084-4735
Pojawia się w:
Physicochemical Problems of Mineral Processing
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Methodology for Implementing Scalable Run-Time Reconfigurable Devices
Autorzy:
Kotynia, Ł.
Amrozik, P.
Napieralski, A.
Powiązania:
https://bibliotekanauki.pl/articles/226469.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
design reuse
floorplanning
FPGA
implementation
verification
reconfigurable logic
timing analysis
Opis:
The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 2; 177-183
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology
Autorzy:
Abdollahi, Hassan
Hooshmand, Reza
Owlia, Hadi
Powiązania:
https://bibliotekanauki.pl/articles/226818.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
current mode logic (CML)
graphene
graphene FET
low-power design
Opis:
In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 381-388
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of Mealy Finite-state Machines with the Transformation of Object Codes
Autorzy:
Barkalov, A. A.
Barkalov, A. A., Jr.
Powiązania:
https://bibliotekanauki.pl/articles/908476.pdf
Data publikacji:
2005
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
programowalny układ logiczny
automat skończony
bramka logiczna
finite state machine
programmable logic device
object
design
logic circuit
Opis:
An optimization method of the logic circuit of a Mealy finite-state machine is proposed. It is based on the transformation of object codes. The objects of the Mealy FSM are internal states and sets of microoperations. The main idea is to express the states as some functions of sets of microoperations (internal states) and tags. The application of this method is connected with the use of a special code converter in the logic circuit of an FSM. An example of application is given. The effectiveness of the proposed method is also studied.
Źródło:
International Journal of Applied Mathematics and Computer Science; 2005, 15, 1; 151-158
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Lightweight PUF-Based Gate Replacement Technique to Reduce Leakage of Information through Power Profile Analysis
Autorzy:
Mohankumar, N.
Jayakumar, M.
Nirmala, Devi M.
Powiązania:
https://bibliotekanauki.pl/articles/2200703.pdf
Data publikacji:
2022
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
Design for Security
Hardware Security
PUF
TRNG
Wave Dynamic Differential Logic
Opis:
The major challenge faced by electronic device designers is to defend the system from attackers and malicious modules called Hardware Trojans and to deliver a secured design. Although there are many cryptographic preventive measures in place adversaries find different ways to attack the device. Differential Power Analysis (DPA) attack is a type of Side Channel Attacks, used by an attacker to analyze the power leakage in the circuit, through which the functionality of the circuit is extracted. To overcome this, a lightweight approach is proposed in this paper using, Wave Dynamic Differential Logic (WDDL) technique, without incurring any additional resource cost and power. The primary objective of WDDL is to make the power consumption constant of an entire circuit by restricting the leakage power. The alternate strategy used by an adversary is to leak the information through reverse engineering. The proposed work avoids this by using a bit sequencer and a modified butterfly PUF based randomizing architecture. A modified version of butterfly PUF is also proposed in this paper, and from various qualitative tests performed it is evident that this PUF can prevent information leakage. This work is validated on ISCAS 85, ISCAS 89 benchmark circuits and the results obtained indicate that the difference in leakage power is found to be very marginal.
Źródło:
International Journal of Electronics and Telecommunications; 2022, 68, 4; 749--754
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low-Power High-Speed Double Gate 1-bit Full Adder Cell
Autorzy:
Kumar, R.
Roy, S.
Bhunia, C. T.
Powiązania:
https://bibliotekanauki.pl/articles/226653.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
low-power full-adder
low-power CMOS design
multiplexer based full-adder design
multi-threshold voltage based full-adder design
pass transmission logic
Opis:
In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 4; 329-334
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Reduction in the number of PAL macrocells in the ciruit of a Moore FSM
Autorzy:
Barkalov, A. A.
Titarenko, L.
Chmielewski, S.
Powiązania:
https://bibliotekanauki.pl/articles/929833.pdf
Data publikacji:
2007
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
Moore finite-state machine
complex programmable logic devices
design
logic circuit
pseudoequivalent states
automat Moore'a
złożone programowalne układy logiczne
układ logiczny
stan pseudorównoważny
Opis:
Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.
Źródło:
International Journal of Applied Mathematics and Computer Science; 2007, 17, 4; 565-575
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The Use of Fuzzy Evaluation and Radical Cut-Off Strategy to Improve Apictorial Puzzle Assembly with Exhaustive Search Algorithm Performance
Autorzy:
Skulimowski, Stanisław
Montusiewicz, Jerzy
Badurowicz, Marcin
Powiązania:
https://bibliotekanauki.pl/articles/2180605.pdf
Data publikacji:
2022
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
fuzzy logic
exhaustive search
reassembling
linguistic methods
puzzle
contour description
fail-fast design
cut-off strategy
Opis:
The paper presents an approach to solving the problem of assembling broken, flat elements using a letter notation of the elements’ contours and checking their matching using linguistic methods. Previous studies with the use of exhaustive search have shown effectiveness in finding possible connections, but they are burdened with a large number of calculations and the time needed to carry them out. In order to accelerate the process of searching for solutions, the possibility of using a fail-fast method of fuzzy assessment of potential combinations of elements was checked, as well as the method of cutting off potential, but not effective connections. The numerical experiment carried out showed a significant reduction in the number of trials and total computation time while maintaining the quality of the potential solutions found.
Źródło:
Advances in Science and Technology. Research Journal; 2022, 16, 2; 179--187
2299-8624
Pojawia się w:
Advances in Science and Technology. Research Journal
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Parallel robot controlled by PLC and its digital twin
Autorzy:
Michalík, R.
Hrbček, J.
Janota, A.
Powiązania:
https://bibliotekanauki.pl/articles/2063983.pdf
Data publikacji:
2021
Wydawca:
Uniwersytet Morski w Gdyni. Wydział Nawigacyjny
Tematy:
digital twin
human machine interface
PLC Controllers
computer aided design
paralled robot
CAD
programmable logic controller
PLC
Opis:
Modern ways of device development use the concept of a digital twin. A digital twin is an accurate digital copy of something that exists or is planned to be realized in the physical world. The digital twin is not only a virtual model of the physical system, but also a dynamic data and status information carrier obtained through a series of IoT-connected sensors that collect data from the physical world and send it to machines. The digital twin provides an overview of what is happening to the device in real time. This is very important in industry as this information is helpful to reduce maintenance issues and ensure production performance. This work focuses on the design and creation of a cybernetic physical system and its digital twin, based on CAD system modeling in conjunction with simulation and programming tools connected to real and simulated control systems. This process accelerates the development of the application implementation with the possibility to create a PLC control program and tune the system already in the design phase. Thus, the physical realization can be done in parallel with the programming and creation of the HMI interface. Modular programming will further accelerate software development [1]. The created system and its digital twin serve as a unified teaching tool without the need for real devices to be used by many students and users. This approach allows testing of program algorithms without the risk of damaging physical devices and is also suitable for distance learning.
Źródło:
TransNav : International Journal on Marine Navigation and Safety of Sea Transportation; 2021, 15, 3; 867--871
2083-6473
2083-6481
Pojawia się w:
TransNav : International Journal on Marine Navigation and Safety of Sea Transportation
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A power-balanced sequential element for the delay-based dual-rail precharge logic style
Autorzy:
Bongiovanni, S
Olivieri, M
Scotti, G.
Trifiletti, A.
Powiązania:
https://bibliotekanauki.pl/articles/397742.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
cryptography
delay-based dual-rail precharge logic
DDPL
dynamic flip-flop
dual-rail precharge logic
power analysis
PA
power-balanced circuits
sense amplifier-based logic
SABL
VLSI design
VLSI
kryptografia
przerzutnik dynamiczny
analiza energetyczna
Opis:
Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is to break the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave flip-flop which is compatible with the DDPL data encoding. Efforts were made in order to design a completely dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover we show that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performance in terms of NED (Normalized Energy Deviation) and CV (Coefficient of Variation) of the current samples as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 4; 129-141
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł

Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies