Temat: heterogeneous programmable structures - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs
Autorzy:: Rawski, M.
Powiązania:: https://bibliotekanauki.pl/articles/226835.pdf
Data publikacji:: 2010
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: distributed arithmetic
FPGA
heterogeneous programmable structures
Opis:: Distributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.
Źródło:: International Journal of Electronics and Telecommunications; 2010, 56, 4; 345-350
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures
Autorzy:: Staworko, M.
Rawski, M.
Powiązania:: https://bibliotekanauki.pl/articles/226414.pdf
Data publikacji:: 2012
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: distributed arithmetic
FPGA
FIR filter
heterogeneous programmable structures
Opis:: Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is help ful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method.
Źródło:: International Journal of Electronics and Telecommunications; 2012, 58, 4; 335-344
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

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