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Wyświetlanie 1-3 z 3
Tytuł:
Endomorphism monoid of diamond product of two common complete bipartite graphs
Autorzy:
Jiarasuksakun, T.
Rutjanisarakul, T.
Thongjua, W.
Powiązania:
https://bibliotekanauki.pl/articles/121678.pdf
Data publikacji:
2010
Wydawca:
Uniwersytet Humanistyczno-Przyrodniczy im. Jana Długosza w Częstochowie. Wydawnictwo Uczelniane
Tematy:
graph theory
bipartite graph
teoria grafów
graf dwudzielny
Opis:
An endomorphism of a graph G = (V, E) is a mapping f : V → V such that for all x, y ∈ V if {x, y} ∈ E, then {f (x),f (y)}∈ E. Let End(G) be the class of all endomorphisms of graph G. The diamond product of graph G = (V, E) (denoted by G ◊ G) is a graph defined by the vertex set V (G ◊ G) = End(G) and the edge set E (G ◊ G) ={{f, g} ⊂ End(G)|{f(x), g(x)} ∈ E for all x ∈ V}. Let Km,n be a complete bipartite graph on m + n vertices. This research aims to study the algebraic property of V (Km,n ◊ Km,n) = End(Km,n) after we have found that Km,n ◊ Km,n is also a complete bipartite graph on mmnn + nmmn vertices. The result shows that all of its vertices (endomorphisms) form a noncommutative monoid.
Źródło:
Scientific Issues of Jan Długosz University in Częstochowa. Mathematics; 2010, 15; 59-66
2450-9302
Pojawia się w:
Scientific Issues of Jan Długosz University in Częstochowa. Mathematics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Digraph-building method for finding a set of minimal realizations of 2-D dynamic systems
Autorzy:
Markowski, K. A.
Hryniów, K.
Powiązania:
https://bibliotekanauki.pl/articles/200035.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
2-D system
characteristic polynomial
digraph
minimal realization
MATLAB
system 2D
wielomian
graf dwudzielny
Opis:
This paper presents a digraph-building method designed to find the determination of realization of two-dimensional dynamic system. The main differences between the method proposed and other state-of-the-art solutions used include finding a set of realizations (belonging to a defined class) instead of only one realization, and the fact that obtained realizations have minimal size of state matrices. In the article, the proposed method is described, compared to state-of-the-art methods and illustrated with numerical examples. To the best of authors’ knowledge, the method shown in the paper is superior to all other state-of-the-art solutions both in terms of number of solutions and their matrix size. Additionally, MATLAB function for determination of realization based on the set of state matrices is included.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2018, 66, 5; 589-597
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models
Autorzy:
Javid, F.
Iskander, R.
Durbin, F.
Louerat, M.-M.
Powiązania:
https://bibliotekanauki.pl/articles/398025.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
IP analogowe
design reuse
graf dwudzielny
model tranzystora
migracja technologii
analog IP
analog sizing
bipartite graphs
transistor compact models
technology migration
Opis:
This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing methodology [1]. They allow to compute transistors sizes and biases based on transistor compact models, while respecting the designer's hypotheses. Computed sizes and biases are accurate, and guarantee the correct electrical behavior as expected by the designer. Sizing and biasing operators interface with a Spice-like simulator, allowing possible use of all available compact models for circuit sizing and biasing over different technologies. A bipartite graph , that contains sizing and biasing operators, is associated to the design view of a circuit, it is the design procedure for the given circuit. To illustrate the effectiveness of the proposed fixed point algorithm, a folded cascode OTA is efficiently sized with a 130nm process, then migrated to a 65nm technology. Both sizing and migration are performed in a few milliseconds.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 1; 7-14
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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