Temat: gate stack - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Composition and electrical properties of ultra-thin SiOxNy layers formed by rf plasma nitrogen implantation/plasma oxidation processes
Autorzy:: Bieniek, T.
Beck, R. B.
Jakubowski, A.
Konarski, P.
Ćwil, M.
Hoffman, P.
Schmeißer, D.
Powiązania:: https://bibliotekanauki.pl/articles/308689.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: CMOS
gate stack
oxynitride
plasma implantation
Opis:: Experiments presented in this work are a summary of the study that examines the possibility of fabrication of oxynitride layers for Si structures by nitrogen implantation from rf plasma only or nitrogen implantation from rf plasma followed immediately by plasma oxidation process. The obtained layers were characterized by means of: ellipsometry, XPS and ULE-SIMS. The results of electrical characterization of NMOS Al-gate test structures fabricated with the investigated layers used as gate dielectric, are also discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 9-15
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
Autorzy:: Bieniek, T.
Beck, R. B.
Jakubowski, A.
Głuszko, G.
Konarski, P.
Ćwil, M.
Powiązania:: https://bibliotekanauki.pl/articles/308685.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: CMOS
dual gate oxide
gate stack
oxynitride
plasma implantation
Opis:: The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 3-8
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Ultrathin oxynitride films for CMOS technology
Autorzy:: Beck, R.B.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/308025.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: MOS technology
gate stack
ultrathin oxynitride layers
high temperature processing
plasma processing
Opis:: In this work, a review of possible methods of oxynitride film formation will be given. These are different combinations of methods applying high-temperature oxidation and nitridation, as well as ion implantation and deposition techniques. The layers obtained using these methods differ, among other aspects in: nitrogen content, its profile across the ultrathin layer,... etc., which have considerable impact on device properties, such as leakage current, channel mobility, device stability and its reliability. Unlike high-temperature processes, which (understood as a single process step) usually do not allow the control of the nitrogen content at the silicon-oxynitride layer interface, different types of deposition techniques allow certain freedom in this respect. However, deposition techniques have been believed for many years not to be suitable for such a responsible task as the formation of gate dielectrics in MOS devices. Nowadays, this belief seems unjustified. On the contrary, these methods often allow the formation of the layers not only with a uniquely high content of nitrogen but also a very unusual nitrogen profile, both at exceptionally low temperatures. This advantage is invaluable in the times of tight restrictions imposed on the thermal budget (especially for high performance devices). Certain specific features of these methods also allow unique solutions in certain technologies (leading to simplifications of the manufacturing process and/or higher performance and reliability), such as dual gate technology for system-on-chip (SOC) manufacturing.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 62-69
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Semiconductor cleaning technology for next generation material systems
Autorzy:: Ruzyllo, J.
Powiązania:: https://bibliotekanauki.pl/articles/308761.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: III-V compounds
FinFET
IC manufacturing
MEMS
MOS gate stack
semiconductor cleaning
Opis:: This paper gives a brief overview of the challenges wafer cleaning technology is facing in the light of advanced silicon technology moving in the direction of non-planar device structures and the need for modified cleans for semiconductors other than silicon. In the former case, the key issue is related to cleaning and conditioning of vertical surfaces in next generation CMOS gate structure as well as deep 3D geometries in MEMS devices. In the latter, an accelerated pace at which semiconductors other than silicon are being introduced into the mainstream manufacturing calls for the development of material specific wafer cleaning technologies. Examples of the problems related to each challenge are considered.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 44-48
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Challenges in scaling of CMOS devices towards 65 nm node
Autorzy:: Jurczak, M.
Veloso, A.
Rooyackers, R.
Augendre, E.
Mertens, S.
Rotschild, A.
Scaekers, M.
Lindsay, R.
Lauwers, A.
Henson, K.
Severi, S.
Pollentier, I.
Keersgieter de, A.
Powiązania:: https://bibliotekanauki.pl/articles/308984.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: CMOS devices
gate dielectrics
shallow junctions
silicide
gate stack
lithography
gate patterning
silicon recess
device integration
Opis:: The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electrical device specifications especially leakage current and the circuit power dissipation.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 3-6
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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