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    Wyświetlanie 1-5 z 5
    Tytuł:
    Some dual logic without tautologies
    Autorzy:
    Górnicka, A.
    Bryll, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/951850.pdf
    Data publikacji:
    2015
    Wydawca:
    Uniwersytet Humanistyczno-Przyrodniczy im. Jana Długosza w Częstochowie. Wydawnictwo Uczelniane
    Tematy:
    podwójna logika
    tautologia
    dual logic
    tautology
    Opis:
    On this paper we consider a logic dual to the logic CRA and prove that it does not contain tautologies.
    Źródło:
    Scientific Issues of Jan Długosz University in Częstochowa. Mathematics; 2015, 20; 39-47
    2450-9302
    Pojawia się w:
    Scientific Issues of Jan Długosz University in Częstochowa. Mathematics
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis of High-Performance Near-threshold Dual Mode Logic Design
    Autorzy:
    Bikki, Pavankumar
    Powiązania:
    https://bibliotekanauki.pl/articles/226748.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS logic
    dual mode logic
    dynamic mode
    high performance
    minimum energy point
    near-threshold
    Opis:
    A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
    Źródło:
    International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A power-balanced sequential element for the delay-based dual-rail precharge logic style
    Autorzy:
    Bongiovanni, S
    Olivieri, M
    Scotti, G.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/397742.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    cryptography
    delay-based dual-rail precharge logic
    DDPL
    dynamic flip-flop
    dual-rail precharge logic
    power analysis
    PA
    power-balanced circuits
    sense amplifier-based logic
    SABL
    VLSI design
    VLSI
    kryptografia
    przerzutnik dynamiczny
    analiza energetyczna
    Opis:
    Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is to break the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave flip-flop which is compatible with the DDPL data encoding. Efforts were made in order to design a completely dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover we show that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performance in terms of NED (Normalized Energy Deviation) and CV (Coefficient of Variation) of the current samples as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2013, 4, 4; 129-141
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On the validity of the definition of a complement-classifier
    Autorzy:
    Stopa, Mariusz
    Powiązania:
    https://bibliotekanauki.pl/articles/1047622.pdf
    Data publikacji:
    2020-12-29
    Wydawca:
    Copernicus Center Press
    Tematy:
    category theory
    topos theory
    categorical logic
    Heyting algebras
    co-Heyting algebras
    intuitionistic logic
    dual to intuitionistic logic
    complement-classifier
    Opis:
    It is well-established that topos theory is inherently connected with intuitionistic logic. In recent times several works appeared concerning so-called complement-toposes (co-toposes), which are allegedly connected to the dual to intuitionistic logic. In this paper I present this new notion, some of the motivations for it, and some of its consequences. Then, I argue that, assuming equivalence of certain two definitions of a topos, the concept of a complement-classifier (and thus of a co-topos as well) is, at least in general and within the conceptual framework of category theory, not appropriately defined. For this purpose, I first analyze the standard notion of a subobject classifier, show its connection with the representability of the functor Sub via the Yoneda lemma, recall some other properties of the internal structure of a topos and, based on these, I critically comment on the notion of a complement-classifier (and thus of a co-topos as well).
    Źródło:
    Zagadnienia Filozoficzne w Nauce; 2020, 69; 111-128
    0867-8286
    2451-0602
    Pojawia się w:
    Zagadnienia Filozoficzne w Nauce
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism
    Autorzy:
    Doligalski, M.
    Adamski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/227254.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    logic controller
    dual specification
    hierarchical Petri net
    UML
    state machine diagram
    Opis:
    Hierarchical Petri nets beside UML state machine diagrams, sequentional function charts (SFC) and hierarchical concurrent state machines are common solution for specification of logic controllers. These specification formats provide both concurrency and modeling on multi levels of abstraction (hierarchic approach). But only state machine diagrams supports exceptions handling in direct way. Program model presented in form of state machine diagram may be later transformed into a program in the SFC language or transformed in the Petri Net and implemented in the FPGA structure. Similarity between SFC language and Petri Nets give us lot of tools for analysis such control system. Article presents new approach for exceptions handling in hierarchical Petri nets as formal specification for logic controllers. Proposed method of specification can be used independently or as a part of dual specification (correlated state machine diagram and hierarchical configurable Petri Net).
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 43-48
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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