- Tytuł:
- 100 Gbps wireless – data link layer VHDL implementation
- Autorzy:
-
Lopacinski, L.
Nolte, J.
Buechner, S.
Brzozowski, M.
Kraemer, R. - Powiązania:
- https://bibliotekanauki.pl/articles/973065.pdf
- Data publikacji:
- 2015
- Wydawca:
- Stowarzyszenie Inżynierów i Techników Mechaników Polskich
- Tematy:
-
data link layer
wireless
100 Gbps
FPGA - Opis:
- In this paper, we describe implementation and hardware used for a wireless 100 Gbps data link layer demonstrator. So fast stream processing requires a highly parallelized approach. The timing requirements of the 100 Gbps networks are so demanding that there is no chance to deal with this task as a single stream in a field programmable gate array (FPGA). Due to this reason, we introduce and validate one of possible architectures that can solve the task. The 100 Gbps implementation is explained in detail, and the most important parameters of the FPGA design are mentioned.
- Źródło:
-
Measurement Automation Monitoring; 2015, 61, 7; 333-336
2450-2855 - Pojawia się w:
- Measurement Automation Monitoring
- Dostawca treści:
- Biblioteka Nauki
Artykuł