Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

Wyszukujesz frazę "common-mode feedback" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
A novel high-swing high-speed with 187 µW power consumption Common-Mode Feedback Block (CMFB) based on rail-to-rail technique
Autorzy:
Mahdavi, S.
Noruzpur, F.
Ghadimi, E.
Khanshan, T. M.
Powiązania:
https://bibliotekanauki.pl/articles/397734.pdf
Data publikacji:
2017
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
common-mode feedback
high-speed
low voltage
folded cascode
high swing
sprzężenie zwrotne dla sygnału wspólnego
niskie napięcie
kaskoda odwrócona
Opis:
This paper presents a new high-swing, high-speed and low power continuous-time Common-Mode Feedback Block (CMFB) based on rail-to-rail technique. The main purposes of the proposed idea are to achieve high-speed, low settling time error, large output swing, and low power as well. Moreover, applying the worst case simulation (initial condition 0 and 1.8 volts) on the proposed CMFB circuit, the output voltage can be settled in the desired level just after 1.18ns noticeably. The settling time error and the power consumption of the suggested common-mode feedback circuit are just 103|iV and 187µW with the power supply of 1.8 volts respectively. Meanwhile, DC gain and phase margin of the amplifier are 74dB and 67 degree correspondingly, and 0.5pF capacitor load is applied to the output nodes of the amplifier. It is noteworthy that, the proposed idea is a good candidate for low voltage applications too. Because it just needs 2 overdrive voltage (AV) to start its performance. Applying the proposed idea on the folded cascode amplifier it achieves SNDR of 68.68dB with the Effective Number of Bits (ENOB) 11.15 bits respectively. The proposed CMFB occupies an active area of 155.58µm2 (10.56µm*14.73µm). Finally, the proposed structure is simulated in whole process corner condition and different temperatures from -70°C to +70°C. Simulation results are performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.
Źródło:
International Journal of Microelectronics and Computer Science; 2017, 8, 2; 50-56
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
Autorzy:
Khatak, Anil
Kumar, Manoj
Dhull, Sanjeev
Powiązania:
https://bibliotekanauki.pl/articles/1844527.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog to digital converter
ADC
successive approximation register (SAR)
common mode current feedback gain boosting
CMFD-GB
residue amplifier
RA
spurious free dynamic range
SFDR
integral nonlinearity
INL
differential nonlinearity
DNL
Opis:
A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

    Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies