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    Wyświetlanie 1-8 z 8
    Tytuł:
    Joint Source-Channel Coding in Dictionary Methods of Lossless Data Compression
    Autorzy:
    Rodziewicz, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/226851.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    joint source-channel coding
    lossless data compression LZ 77
    LZSS
    source coding
    Opis:
    Limitations on memory and resources of communications systems require powerful data compression methods. Decompression of compressed data stream is very sensitive to errors which arise during transmission over noisy channels, therefore error correction coding is also required. One of the solutions to this problem is the application of joint source and channel coding. This paper contains a description of methods of joint source-channel coding based on the popular data compression algorithms LZ'77 and LZSS. These methods are capable of introducing some error resiliency into compressed stream of data without degradation of the compression ratio. We analyze joint source and channel coding algorithms based on these compression methods and present their novel extensions. We also present some simulation results showing usefulness and achievable quality of the analyzed algorithms.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 351-355
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipeline processing in low-density parity-check codes hardware decoder
    Autorzy:
    Sułek, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/202316.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    LDPC codes
    iterative decoding
    decoder implementation
    pipelined processing
    Opis:
    Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation – and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2011, 59, 2; 149-155
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    High-Rate Permutation Coding with Unequal Error Protection
    Autorzy:
    Ogunyanda, Kehinde
    Swart, Theo G.
    Ogunyanda, Opeyemi O.
    Powiązania:
    https://bibliotekanauki.pl/articles/2055239.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    high-rate codes
    permutation codes
    power line communications
    unequal error protection
    Opis:
    Channel coding provides numerous advantages to digital communications. One of such advantages is error correcting capabilities. This, however, comes at the expense of coding rate, which is a function of the codebook’s cardinality |C| or number of coded information bits and the codeword length M. In order to achieve high coding rate, we hereby report a channel coding approach that is capable of error correction under power line communications (PLC) channel conditions, with permutation coding as the coding scheme of choice. The approach adopts the technique of unequal error correction for binary codes, but with the exception that non-binary permutation codes are employed here. As such, certain parts of the information bits are coded with permutation symbols, while transmitting other parts uncoded. Comparisons with other conventional permutation codes are presented, with the proposed scheme exhibiting a relatively competitive performance in terms of symbol error rate.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 1; 27--33
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A solution for increasing data rate of Doppler-RAKE system
    Autorzy:
    Nguyen Nguyen, M.
    Modelski, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/307797.pdf
    Data publikacji:
    2003
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    diversity
    Doppler-RAKE
    CDMA
    multi-path
    fast-fading
    spread-time signaling
    multi-user detection
    channel coding
    Opis:
    Doppler-RAKE detection in the CDMA system has been further developed and offers better performances in comparison to conventional RAKE detection, especially in fast-fading environments. Also, the multi-user Doppler-RAKE system works more effectively with channel coding applications. However, by means of exploring the Doppler effect, the system's data rate is decreased. We propose a simple solution to increase the data rate for the system while keeping the Doppler gain.
    Źródło:
    Journal of Telecommunications and Information Technology; 2003, 3; 130-134
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Konfigurowalny dekoder kodów LDPC implementowany w układzie FPGA
    Configurable LDPC decoder implemented in FPGA device
    Autorzy:
    Sułek, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/151906.pdf
    Data publikacji:
    2009
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    kody blokowe
    kodowanie kanałowe
    kody LDPC
    dekodowanie iteracyjne
    dekoder LDPC
    block codes
    channel coding
    LDPC codes
    iterative decoding
    LDPC decoder
    Opis:
    Kody LDPC są jednymi z najlepszych znanych klas kodów nadmiarowych, służących do korekcji błędów w kanale telekomunikacyjnym. W niniejszej pracy zaprezentowano opisany w języku VHDL konfigurowalny dekoder podklasy kodów LDPC zorientowanych na efektywną sprzętową implementację. Możliwe jest dostosowanie dekodera dla dowolnego kodu LDPC ze zdefiniowanej podklasy, jak również konfiguracja pewnych parametrów dekodera decydujących o jego własnościach strukturalnych oraz własnościach korekcyjnych systemu. W artykule przedstawiono możliwości konfiguracji dekodera oraz wyniki implementacji: zasoby strukturalne oraz przepustowość dla kilku wybranych kodów.
    The group of Low-Density Parity-Check (LDPC) codes is one of the best known error correcting coding methods that are capable of achieving very low bit error rates at code rates approaching Shannon's channel capacity limit. The article concerns the configurable decoder for a subclass of LDPC codes that are implementation oriented. The decoder has a form of synthesizable VHDL description. It can be adjusted for decoding any code from defined subclass, called Architecture Aware LDPC (AA-LDPC). Configuration of some decoder parameters (message calculating algorithm, message wordlength) is possible as well. These parameters affect decoder structural properties and on the other hand - error correcting performance of the coding system. A number of modifications in the VHDL source code are required to adjust the decoder to the particular AA-LDPC code. These modifications can be made automatically by a software that has been created using Matlab tool. The user needs only to specify the parity check matrix that has architecture-aware structure as well as to specify other parameters of the decoder, such as: message wordlength, maximum number of iteration, the number of computing units (SISO) and the SISO message update (sub-optimal) algorithm. Based on these parameters, automatic generation of synthesizable VHDL description can be performed by the software tool that has been created. The decoder is implemented with the Xilinx VirtexII FPGA device. The simulation environment, making use of the hardware decoder is a base of the platform for fast simulation of the developed LDPC coding systems performance. In this paper we present mainly the decoder reconfiguration methods. Implementation results: structural resources and decoder throughput for a couple of different codes are presented as well.
    Źródło:
    Pomiary Automatyka Kontrola; 2009, R. 55, nr 8, 8; 606-608
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The design of structured LDPC codes with algorithmic graph construction
    Autorzy:
    Sułek, Wojciech
    Powiązania:
    https://bibliotekanauki.pl/articles/2173691.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    low density parity check code
    LDPC
    nonbinary code
    quasi-cyclic code
    kodowanie kanałowe
    kodowanie niebinarne
    kodowanie quasi-cykliczne
    kodowanie korekcyjne
    Opis:
    Low-Density Parity-Check (LDPC) codes are among the most effective modern error-correcting codes due to their excellent correction performance and highly parallel decoding scheme. Moreover, the nonbinary extension of such codes further increases performance in the short-block regime. In this paper, we review the key elements for the construction of implementation-oriented binary and nonbinary codes. These Quasi-Cyclic LDPC (QC-LDPC) codes additionally feature efficient encoder and decoder implementation frameworks. We then present a versatile algorithm for the construction of both binary and nonbinary QC-LDPC codes that have low encoding complexity and an optimized corresponding graph structure. Our algorithm uses a progressive edge growth algorithm, modified for QC-LDPC graph construction, and then performs an iterative global search for optimized cyclic shift values within the QC-LDPC circulants. Strong error correction performance is achieved by minimizing the number of short cycles, and cycles with low external connectivity, within the code graph. We validate this approach via error rate simulations of a transmission system model featuring an LDPC coder-decoder, digital modulation, and additive white Gaussian noise channels. The obtained numerical results validate the effectiveness of the proposed construction algorithm, with a number of constructed codes exhibiting either similar or superior performance to industry standard binary codes and selected nonbinary codes from the literature.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2022, 70, 4; art. no. e141592
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Method for Determining Broadcaster Advised Emergency Wake-up Signal for ISDB-T Digital Television Receivers
    Autorzy:
    Takahashi, Satoshi
    Powiązania:
    https://bibliotekanauki.pl/articles/308586.pdf
    Data publikacji:
    2019
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    binary asymmetric channel
    emergency warning system (EWS)
    intermittent reception
    transmission and modulation coding configuration (TMCC)
    Opis:
    There is a way to automatically wake up television receivers when a broadcaster sends out an emergency alert. In the Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) digital television standard, the emergency wake-up procedure is called an Emergency Warning System (EWS). In ISDB-T, the special signal is embedded in a control message known as transmission and modulation configuration control (TMCC). However, improper identification of the wake-up signal, often encountered in mobile reception, leads to unnecessary wake ups. In this paper, a method of reliably determining a wake-up signal is proposed by assuming that broadcasters will not change the TMCC message except for the wake-up signal when the broadcaster sends out an emergency alert. A change in the wake-up bit leads to variation parity, and the proposed method also relies on such variations. Mutual information to be obtained by the wake-up receiver is evaluated using the memoryless binary asymmetric channel model. Results showed that the proposed method provided mutual information even at a Eb/N₀ being lower than 10 dB. Mutual information of the proposed method with intermittent reception is also analyzed as a function of the duty ratio of the intermittent receiver.
    Źródło:
    Journal of Telecommunications and Information Technology; 2019, 1; 103-112
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Improving the Efficiency of UAV Communication Channels in the Context of Electronic Warfare
    Autorzy:
    Semendiai, Serhii
    Tkach, Yuliіa
    Shelest, Mykhailo
    Korchenko, Oleksander
    Ziubina, Ruslana
    Veselska, Olga
    Powiązania:
    https://bibliotekanauki.pl/articles/27311946.pdf
    Data publikacji:
    2023
    Wydawca:
    Polska Akademia Nauk. Czasopisma i Monografie PAN
    Tematy:
    cognitive radio
    software-defined radio
    neural networks
    coding
    electronic warfare
    communication channel
    wireless communications
    spectrum analysis
    Opis:
    The article is devoted to the development of a method for increasing the efficiency of communication channels of unmanned aerial vehicles (UAVs) in the conditions of electronic warfare (EW). The author analyses the threats that may be caused by the use of electronic warfare against autonomous UAVs. A review of some technologies that can be used to create original algorithms for countering electronic warfare and increasing the autonomy of UAVs on the battlefield is carried out. The structure of modern digital communication systems is considered. The requirements of unmanned aerial vehicle manufacturers for onboard electronic equipment are analyzed, and the choice of the hardware platform of the target radio system is justified. The main idea and novelty of the proposed method are highlighted. The creation of a model of a cognitive radio channel for UAVs is considered step by step. The main steps of modelling the spectral activity of electronic warfare equipment are proposed. The main criteria for choosing a free spectral range are determined. The type of neural network for use in the target cognitive radio system is substantiated. The idea of applying adaptive coding in UAV communication channels using multicomponent turbo codes in combination with neural networks, which are simultaneously used for cognitive radio, has been further developed.
    Źródło:
    International Journal of Electronics and Telecommunications; 2023, 69, 4; 727--732
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-8 z 8

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