Temat: cascode - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Prospects and Development of Vertical Normally-off JFETs in SiC
Autorzy:: Bakowski, M.
Powiązania:: https://bibliotekanauki.pl/articles/308249.pdf
Data publikacji:: 2009
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: JFET cascode
normally-off
SiC
vertical JFET
Opis:: This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25 C degree to 250 C degree. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.
Źródło:: Journal of Telecommunications and Information Technology; 2009, 4; 25-36
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

Artykuł

Zmień widok

na półce

Skocz do pozycji: 2.

Tytuł:: Evaluation of gate drive circuit effect in cascode GaN-based applications
Autorzy:: Tan, Q. Y.
Narayanan, E. M. S.
Powiązania:: https://bibliotekanauki.pl/articles/2173545.pdf
Data publikacji:: 2021
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: cascode GaNFETs
parasitics
buck converter
gate drive design
kaskoda GaNFETs
przetwornica
pasożytnictwo
projekt napędu bramy
Opis:: This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; art. no. e136742
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

Artykuł

Zmień widok

na półce

Skocz do pozycji: 3.

Tytuł:: Evaluation of gate drive circuit effect in cascode GaN-based applications
Autorzy:: Tan, Q. Y.
Narayanan, E. M. S.
Powiązania:: https://bibliotekanauki.pl/articles/2128152.pdf
Data publikacji:: 2021
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: cascode GaNFETs
parasitics
buck converter
gate drive design
kaskoda GaNFETs
przetwornica
pasożytnictwo
projekt napędu bramy
Opis:: This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; e136742, 1--7
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

Artykuł

Zmień widok

na półce

Skocz do pozycji: 4.

Tytuł:: Cascode ampliﬁers with low-gain variability and gain enhancement using a body-biasing technique
Autorzy:: Pereira, N
Oliveira, L. B.
Goes, J.
Oliveira, J. P.
Powiązania:: https://bibliotekanauki.pl/articles/398063.pdf
Data publikacji:: 2013
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: ampliﬁer
body-biasing
cascode
CMOS analog circuits
PVT compensation
wzmacniacz
kaskoda
układy analogowe CMOS
kompensacja PVT
Opis:: This paper presents a simple circuit technique to reduce gain variability with PVT variations in cascode ampliﬁers using a body-biasing scheme, while enhancing the overall gain of the ampliﬁer. Simulation results of a standard telescopic-cascode ampliﬁer, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that the proposed compensated circuit ampliﬁer exhibits a (DC) gain variability smaller (below ± 0.5 dB) than the original (uncompensated) circuit, while reaching a gain enhancement of about 3 dB. The required auxiliary biasing circuit dissipates around 5% of the main ampliﬁer circuit.
Źródło:: International Journal of Microelectronics and Computer Science; 2013, 4, 3; 98-102
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Zmień widok

na półce

Skocz do pozycji: 5.

Tytuł:: A novel high-swing high-speed with 187 µW power consumption Common-Mode Feedback Block (CMFB) based on rail-to-rail technique
Autorzy:: Mahdavi, S.
Noruzpur, F.
Ghadimi, E.
Khanshan, T. M.
Powiązania:: https://bibliotekanauki.pl/articles/397734.pdf
Data publikacji:: 2017
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: common-mode feedback
high-speed
low voltage
folded cascode
high swing
sprzężenie zwrotne dla sygnału wspólnego
niskie napięcie
kaskoda odwrócona
Opis:: This paper presents a new high-swing, high-speed and low power continuous-time Common-Mode Feedback Block (CMFB) based on rail-to-rail technique. The main purposes of the proposed idea are to achieve high-speed, low settling time error, large output swing, and low power as well. Moreover, applying the worst case simulation (initial condition 0 and 1.8 volts) on the proposed CMFB circuit, the output voltage can be settled in the desired level just after 1.18ns noticeably. The settling time error and the power consumption of the suggested common-mode feedback circuit are just 103|iV and 187µW with the power supply of 1.8 volts respectively. Meanwhile, DC gain and phase margin of the amplifier are 74dB and 67 degree correspondingly, and 0.5pF capacitor load is applied to the output nodes of the amplifier. It is noteworthy that, the proposed idea is a good candidate for low voltage applications too. Because it just needs 2 overdrive voltage (AV) to start its performance. Applying the proposed idea on the folded cascode amplifier it achieves SNDR of 68.68dB with the Effective Number of Bits (ENOB) 11.15 bits respectively. The proposed CMFB occupies an active area of 155.58µm² (10.56µm*14.73µm). Finally, the proposed structure is simulated in whole process corner condition and different temperatures from -70°C to +70°C. Simulation results are performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.
Źródło:: International Journal of Microelectronics and Computer Science; 2017, 8, 2; 50-56
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Zmień widok

na półce

Informacja

Wyszukujesz frazę "cascode" wg kryterium: Temat

Źródło danych

Dostawca treści

Kolekcja

Rok wydania

Wydawca

Temat

Autor

Typ dokumentu

Język