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Wyszukujesz frazę "analog design" wg kryterium: Temat


Wyświetlanie 1-6 z 6
Tytuł:
Dynamically programmable analog arrays in acoustic frequency range signal processing
Autorzy:
Falkowski, P.
Mechler, A.
Powiązania:
https://bibliotekanauki.pl/articles/221037.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
FPAA
audio processing
switched-capacitor
analog circuits design
Opis:
Field programmable analog arrays (FPAA), thanks to their flexibility and reconfigurability, give the designers quite new possibilities in analog circuit design. The number of both academic projects on FPAA and applications of commercially available programmable devices is still growing. This paper explores the properties and parameters of two most popular FPAA circuits: the AnadigmVortex AN221E04 and AnadigmApex AN231E04 from the Anadigm company. The research conducted by the authors led to the discovery of some undocumented features of these devices. Several applications for audio processing were built and tested. The results show that these circuits can be used in medium-demanding audio applications. Thanks to dynamic reconfigurability, they also allow to build an universal analog audio signal processor. These circuits can also act as a versatile platform for rapid prototyping and educational purposes.
Źródło:
Metrology and Measurement Systems; 2011, 18, 1; 77-89
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Material, information and formation in parametric design. Experiments in the research laboratory of the students of the faculty of architecture of Poznan University of Technology
Autorzy:
Januszkiewicz, K.
Pawlak, J.
Powiązania:
https://bibliotekanauki.pl/articles/398575.pdf
Data publikacji:
2014
Wydawca:
Politechnika Białostocka. Oficyna Wydawnicza Politechniki Białostockiej
Tematy:
tworzywo
format
eksperyment
narzędzia cyfrowe
digital tools
parametric design
analog design
material
performance
information
formation
experimentation
Opis:
Several experiments combining analog design with digital parametric design have been presented, where the relationship between material properties and the designed shape of an architectural element play an important role. This approach allows to create digital material formations or to structure freeform surfaces, control their tectonics, through parametric modulation. Similar research tasks were initiated in the years 2003-2004 during the classes conducted at the Architectural Associations School of Architecture in London. In Poland, for the first time, making use of that experience, a number of similar teaching experiments were carried out in 2013 under the academic supervision of Krystyna Januszkiewicz and Mateusz Zwierzycki, at the newly established Research Laboratory of the students of the Faculty of Architecture of Poznan University of Technology.
Źródło:
Architecturae et Artibus; 2014, 6, 1; 19-22
2080-9638
Pojawia się w:
Architecturae et Artibus
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analog Circuit Based on Computational Intelligence Techniques
Autorzy:
Oltean, G.
Hintea, S.
Şipos, E.
Powiązania:
https://bibliotekanauki.pl/articles/385049.pdf
Data publikacji:
2009
Wydawca:
Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
Tematy:
analog circuit design
optimization
genetic algorithm
neuro-fuzzy systems
Opis:
This paper presents a new method for analog circuit design optimization. Our approach turns to good account the advantages offered by computational intelligence techniques. Design objectives can be expressed in a flexible manner using fuzzy sets. This way appears the possibility to consider different degrees for requirement achievements and acceptability degree for a particular solution. Neuro-fuzzy systems (universal approximators) are used to model the complex multi-variable and nonlinear circuit performances. These models satisfy two main requirements: high accuracy and low computation complexity. An efficient and robust genetic algorithm does avoiding local minima the exploration of the large, multidimensional solution space in quest for the optimal solution.
Źródło:
Journal of Automation Mobile Robotics and Intelligent Systems; 2009, 3, 2; 63-69
1897-8649
2080-2145
Pojawia się w:
Journal of Automation Mobile Robotics and Intelligent Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models
Autorzy:
Javid, F.
Iskander, R.
Durbin, F.
Louerat, M.-M.
Powiązania:
https://bibliotekanauki.pl/articles/398025.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
IP analogowe
design reuse
graf dwudzielny
model tranzystora
migracja technologii
analog IP
analog sizing
bipartite graphs
transistor compact models
technology migration
Opis:
This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing methodology [1]. They allow to compute transistors sizes and biases based on transistor compact models, while respecting the designer's hypotheses. Computed sizes and biases are accurate, and guarantee the correct electrical behavior as expected by the designer. Sizing and biasing operators interface with a Spice-like simulator, allowing possible use of all available compact models for circuit sizing and biasing over different technologies. A bipartite graph , that contains sizing and biasing operators, is associated to the design view of a circuit, it is the design procedure for the given circuit. To illustrate the effectiveness of the proposed fixed point algorithm, a folded cascode OTA is efficiently sized with a 130nm process, then migrated to a 65nm technology. Both sizing and migration are performed in a few milliseconds.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 1; 7-14
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors
Autorzy:
Passos, F.
Fino, M. H.
Moreno, E. R.
Powiązania:
https://bibliotekanauki.pl/articles/226450.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
inductor design
variable width integrated spiral inductor
integrated spiral inductor
CMOS analog circuits
IC designing
RF IC design
Opis:
In this paper a general method for the determination of the series inductance of polygonal tapered inductor s is presented. The value obtained can be integrated into any integrated inductor lumped element model, thus granting the overall characterization of the device and the evaluation of performance parameters such as the quality factor or the resonance frequency. In this work, the inductor is divided into several segments and the corresponding self and mutual inductances are calculated. In the end, results obtained for several working examples are compared against electromagnetic (EM) simulations are performed in order to check the validity of the model for square, hexagonal, octagonal and tapered inductors. The proposed method depends exclusively on the geometric characteristics of the inductor as well as the technological parameters. This allows its straight forward application to any inductor shape or technology.
Źródło:
International Journal of Electronics and Telecommunications; 2014, 60, 1; 73-77
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
VHDL-Ams Model of the Integrated Membrane Micro-Accelerometer with Delta-Sigma (Δσ) Analog-To-Digital Converter for Schematic Design Level
Autorzy:
Golovatyj, А.
Teslyuk, V.
Kryvyy, R.
Powiązania:
https://bibliotekanauki.pl/articles/411400.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Oddział w Lublinie PAN
Tematy:
Micro-Electro-Mechanical Systems (MEMS)
micromechanical sensitive element
integrated membrane micro-accelerometer
delta-sigma modulation
pulse width modulation (PWM)
delta-sigma analog-todigital converter (ADC)
one bit digital-to-analog converter (DAC)
VHDL-AMS hardware description language
hAMSter software
schemotechnical design level
Opis:
VHDL-Ams model of integrated membrane type micro-accelerometer with delta-sigma (ΔΣ) analog-to-digital converter for schematic design level was developed. It allows simulating movement of the sensitive element working weigh from the applied acceleration, differential capacitor and original signal capacity change, signal digitizing with the help of DeltaSigma ADC with defined micro-accelerometer structural parameters, and analyzze an integrated device at the schemotechnical design level.
Źródło:
ECONTECHMOD : An International Quarterly Journal on Economics of Technology and Modelling Processes; 2015, 4, 2; 65-70
2084-5715
Pojawia się w:
ECONTECHMOD : An International Quarterly Journal on Economics of Technology and Modelling Processes
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-6 z 6

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