Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

English (EN)·Polski (PL)·Yкраїнський (UK)
Przejdź do strony domowej biblioteki Centralna Biblioteka Wojskowa Link otwiera się w nowym oknie Logo biblioteki Prolib Integro - strona głównaCentralna Biblioteka Wojskowa

Wyszukujesz frazę "Verilog-A" wg kryterium: Temat

  Lista filtrów
Wyrównaj
    Wyświetlanie 1-8 z 8
    Tytuł:
    A Qucs/QucsStudio swept parameter technique for statistical circuit simulation
    Autorzy:
    Brinson, M. E.
    Powiązania:
    https://bibliotekanauki.pl/articles/397903.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    QucsStudio
    Qucs
    statistical circuit simulation
    swept parameter lists
    Verilog-A compact semiconductor device models
    statystyczna symulacja obwodu
    Verilog-A
    Opis:
    Qucs and QucsStudio open source circuit simulators have a wealth of built in swept data features, including facilities for linear and logarithmic scans of simulation variables and for setting component values and device parameters. These simulators also allow semicolon separated lists of numerical values to be used as swept data. This little known feature provides a very flexible mechanism for generating component and device parameter statistical data. An outline of a statistical circuit simulation technique is presented in this paper. The proposed technique can be used with any general purpose circuit simulator equipped with swept data capabilities and as such is suitable for the study of device and circuit performance resulting from variations in device parameters and component values. The operation of the proposed simulation technique is illustrated with the results from an investigation of the statistical performance of a simple MOS current mirror integrated circuit cell, modeled with a speed optimized Verilog-A version of a long channel EPFL_EKV v2.6 MOS transistor model.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2013, 4, 3; 92-97
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A rapid analysis of very short channel MOSFET performances by using a dynamic simple model
    Autorzy:
    Rabhi, A.
    El`Hadj Bekka, R.
    Benhamadouche, A.
    Rahmoune, F.
    Charlot, J.-J.
    Powiązania:
    https://bibliotekanauki.pl/articles/398108.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    model tranzystora polowego MOS
    MOSFET modeling
    BSIM3V3
    Verilog-A
    Opis:
    A simplified MOSFET model is presented in this paper. The performances of the model, UNICELL (Unique Cell Model), are compared to those provided by BSIM3V3 taken as reference, even for very short channel length MOSFET (45 nm). It is shown that using only two UNICELL cells (BICELL) gives a good deal for CAD static and dynamic usage, because of the few number of parameters to be used in comparison to BSIM3. BICELL can also be used for determining internal performance analysis.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 3; 225-228
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Verilog-A inductor compact model for the efficient simulation of Class-D VCOs
    Autorzy:
    Fino, M. H.
    Powiązania:
    https://bibliotekanauki.pl/articles/397955.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    Verilog-A
    RF modeling
    tapered Inductor
    Class D Oscillator
    modelowanie RF
    cewka indukcyjna
    oscylator
    Opis:
    This paper presents the use of a Verilog-A compact model for integrated spiral inductors, for the simulation of Class-D CMOS oscillators. The model takes into consideration the geometric parameters characterizing the inductor layout, as well as the technological parameters. The accuracy of the model is checked against simulations with ASITIC simulator and limitations of the model are established. The model is integrated into Cadence environment, offering the designer the possibility to efficiently simulate radio frequency blocks considering the non-idealities of both the inductors and the transistors in nanometric technologies. The particular case for a class-D oscillator is illustrated.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 3; 114-118
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Verilog-A Compact Semiconductor Device Modelling and Circuit Macromodelling with the QucsStudio-ADMS "Turn-Key" Modelling System
    Autorzy:
    Brinson, M. E.
    Margraf, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/398029.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    QucsStudio
    ADMS
    Verilog-A
    modelowanie turn-key
    compact device modelling
    turn-key component modeling
    Opis:
    The Verilog-A "Analogue Device Model Synthesizer" (ADMS) has in recent years become an established modelling tool for GNU General Public License circuit simulator development. Qucs and ngspice are two examples of open source circuit simulators that employ ADMS for compact semiconductor model construction. This paper presents a "turn- key" compact device modelling and circuit macromodelling system based on ADMS and implemented in the QucsStudio circuit design, simulation and manufacturing environment. A core feature of the new system is a modelling procedure which does not require users to manually patch, by hand, circuit simulator C++ code. At the start of QucsStudio simulation the software automatically detects any changes in Verilog-A model code, re-compiling and dynamically linking the modified code to the body of the QucsStudio cod e. The inherent flexibility of the "turn-key" system encourage s rapid experimentation with analogue and RF compact device models and circuit macromodels. In this paper QucsStudio "turn-key" modelling is illustrated by the design of a single stage RF amplifier circuit and the Harmonic Balance large signal AC simulation of a 50 Ω RF diode switch.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 1; 32-40
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Current conveyor equation-defined macromodels for wideband RF circuit design
    Autorzy:
    Brinson, M.
    Kuznetsov, V.
    Powiązania:
    https://bibliotekanauki.pl/articles/397845.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    Qucs
    current conveyors
    compact semiconductor device modelling
    equation-defined devices
    macromodels
    Verilog-A module synthesis
    konwejer prądowy
    modelowanie urządzeń półprzewodnikowych
    makromodele
    Opis:
    A high percentage of analogue integrated circuit designs use voltage domain signal processing techniques. Given the fact that integrated circuit current conveyors are high bandwidth current processing devices, often with superior RF performance compared to comparable voltage domain devices, it is surprising that the number of current mode integrated circuits available, as standard of-the-shelf industrial items, is so small. This paper introduces equation-defined device and Verilog-A synthesis approaches to the macromodelling of current conveyor integrated circuits. To illustrate the proposed modelling techniques the properties of a number of modular behavioural level current conveyor macromodel cells are described and their performance compared. The material presented is intended for analogue device modellers and circuit designers who wish to simulate large signal current domain integrated circuit designs. It also demonstrates how synthesized Verilog-A modules can be derived from equation-defined device and conventional subcircuits to form functional, computationally efficient current conveyor macromodels. To illustrate the application of behavioural current conveyor macromodels the design of a six cell CCII+ instrumentation amplifier is introduced and its performance discussed.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2017, 8, 2; 65-71
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Surface Potential Modeling of a High-k HfO2-Ta2O5 Capacitor in Verilog-A
    Autorzy:
    Angelov, G. V.
    Powiązania:
    https://bibliotekanauki.pl/articles/397997.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    modelowanie elementów elektronicznych
    model kompaktowy
    PSP
    symulacja obwodu
    dielektryk bramkowy o wysokiej przenikalności elektrycznej
    Verilog-A
    Spectre
    device modeling
    compact models
    circuit simulation
    high-k gate dielectric
    Opis:
    A compact model of a high-k HfO2-Ta2O5 mixed layer capacitor stack is developed in Matlab. Model equations are based on the surface potential PSP model. After fitting the C-V characteristics in Matlab the model is coded in Verilog-A hardware description language and it is implemented as external library in Spectre circuit simulator within Cadence CAD system. The results are validated against the experimental measurements of the HfO2-Ta2O5 stack structure.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 3; 111-118
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Modeling the characteristics of high-k HfO2-Ta2O5 capacitor in Verilog-A
    Autorzy:
    Angelov, G. V.
    Powiązania:
    https://bibliotekanauki.pl/articles/398142.pdf
    Data publikacji:
    2011
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    modelowanie elementów elektronicznych
    model kompaktowy
    symulacja obwodu
    dielektryk bramkowy o wysokiej przenikalności elektrycznej
    Verilog-A
    Spectre
    device modeling
    compact models
    circuit simulation
    high-k gate dielectric
    Opis:
    A circuit simulation model of a MOS capacitor with high-k HfO2-Ta2O5 mixed layer is developed and coded in Verilog-A hardware description language. Model equations are based on the BSIM3v3 model core. Capacitance-voltage (C-V) and current-voltage (I-V) characteristics are simulated in Spectre circuit simulator within Cadence CAD system and validated against experimental measurements of the HfO2-Ta2O5 slack structure.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2011, 2, 3; 105-112
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Adaptive EPFL-EKV Long and Short Channel MOS Device Models for Qucs, SPICE and Modelica Circuit Simulation
    Autorzy:
    Brinson, M. E.
    Nabijou, H.
    Powiązania:
    https://bibliotekanauki.pl/articles/398007.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    model adaptacyjny MOS
    Qucs
    SPICE
    Modelica
    monitoring parametru
    adaptive MOS models
    equation-defined device modelling
    Verilog-A
    EPFL-EKV MOS-FET model
    parameter and equation monitoring
    EPFL-EKV MOS-FET
    Opis:
    Equation-defined non-linear functional elements are important building blocks in the development of compact semiconductor device models. Current trends in compact device modelling suggest widespread acceptance among the modeling community of Verilog-A, for semiconductor device specification, model exchange and circuit simulation. This paper outlines techniques for the development of adaptive EPFL-EKV long and short channel MOS models which stress user selectable model features and diagnostic capabilities. Adaptive EPFL-EKV nMOS models based on Verilog-A and Modelica are introduced and their performance compared with simulation data obtained using the "Quite universal circuit simulator" (Qucs), SPICE and the Modelica simulation environment.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 1; 1-6
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-8 z 8

      Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies