- Tytuł:
- A Hardware-Efficient Structure of Complex Numbers Divider
- Autorzy:
-
Cariow, A.
Cariowa, G. - Powiązania:
- https://bibliotekanauki.pl/articles/114589.pdf
- Data publikacji:
- 2017
- Wydawca:
- Stowarzyszenie Inżynierów i Techników Mechaników Polskich
- Tematy:
-
complex-number divider
hardware complexity reduction
VLSI implementation - Opis:
- In this correspondence an efficient approach to structure of hardware accelerator for calculating the quotient of two complex-numbers with reduced number of underlying binary multipliers is presented. The fully parallel implementation of a complex-number division using the conventional approach to structure organization requires 4 multipliers, 3 adders, 2 squarers and 2 divider while the proposed structure requires only 3 multipliers, 6 adders, 2 squarers and 2 divider. Because the hardware complexity of a binary multiplier grows quadratically with operand size, and the hardware complexity of an binary adder increases linearly with operand size, then the complex-number divider structure containing as little as possible embedded multipliers is preferable.
- Źródło:
-
Measurement Automation Monitoring; 2017, 63, 6; 212-213
2450-2855 - Pojawia się w:
- Measurement Automation Monitoring
- Dostawca treści:
- Biblioteka Nauki
Artykuł