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Tytuł:
Proces pomiaru w przetworniku A/C typu Sigma-Delta
Measurement process in Sigma-Delta AD converter
Autorzy:
Jakubiec, J.
Powiązania:
https://bibliotekanauki.pl/articles/152012.pdf
Data publikacji:
2008
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
przetwornik Sigma-Delta
kwantowanie
błąd pomiaru
sigma-delta converter
quantization
measurement error
Opis:
Działania realizowane przez przetwornik A/C typu Sigma-Delta opisano w artykule jako proces pomiaru podzielony na trzy etapy: przetwarzanie analogowe, kwantowanie i przetwarzanie cyfrowe. Poddano analizie podstawowe źródła błędu, a następnie określono wpływ decymacji i filtracji na właściwości wypadkowego błędu wyniku pomiaru. Rozważania analityczne zilustrowano wynikami symulacji uzyskanymi przy użyciu metody Monte Carlo.
A basic scheme of a Sigma-Delta AD converter, analyzed in the paper, is shown in Fig. 1. The converter performs a quantization process, which can be described as compensation of the charge, delivered to the integrator from the source of the measured voltage Ux, with quanta of charge obtained synchronously with clock CLK when the switch P is closed. Value of a charge quantum is given by Eq. (1) and the balance state of the quantizer by Eq. (2). Basing on this equation one can obtain expression (3) describing a measurement result and Eq. (4) that describes value of a voltage quantum. All stages of the processing made by Sigma-Delta converter, i.e. analog conversion, quantization and digital processing, are shown in Fig. 3. One can distinguish three main error sources in this process - input error described by Eq. (6) and two errors connected with quantization: quantization error and standard error caused by dispersion of the quanta values (Eqs. (8), (9) and Fig. 3). Next considerations deal with analysis of decimation and averaging influence on the quantization error and the standard error. Fig. 4 shows exemplary histogram of the quantization error after averaging and Fig. 5 the error being the result of composition of both mentioned errors. Having the errors described one can calculate uncertainty of a measurement result using the procedure presented in paper [3].
Źródło:
Pomiary Automatyka Kontrola; 2008, R. 54, nr 6, 6; 343-346
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool
Autorzy:
Śniatała, P.
Naumowicz, M.
Handkiewicz, A.
Szczęsny, S.
Melo, J. L. A.
Paulino, N.
Goes, J.
Powiązania:
https://bibliotekanauki.pl/articles/201254.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
sigma-delta
current comparator
CAE
komparator
Opis:
The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2015, 63, 4; 919-922
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analiza własności metrologicznych przetworników A/D zbudowanych na bazie modulatorów sigma-delta różnych rzędów
Metrological analysis of A/D converters with sigma-delta modulators of different orders
Autorzy:
Sidor, T.
Powiązania:
https://bibliotekanauki.pl/articles/156804.pdf
Data publikacji:
2014
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
modulator sigma-delta
przetwornik A/D
błąd kwantyzacji
A/D converters
sigma-delta modulators
quantization errors
Opis:
W artykule porównano własności metrologiczne przetworników A/D z modulatorami sigma-delta pierwszego i drugiego rzędu stosując analizę w dziedzinie czasu. Wykazano, że przetworniki z modulatorami wyższych rzędów, wykazują w istocie ten sam poziom błędów kwantowania, co przetworniki z modulatorem pierwszego rzędu. Zwrócono również uwagę na istotne niekonsekwencje, pojawiające się w licznych opracowaniach na ten temat, które posługują się analizą w dziedzinie częstotliwości.
In this paper the time domain analysis is used to compare metrological properties of sigma-delta A/D converters with first order modulator and converters with modulators of higher order. Modulators of higher orders are widely advertised for such converters to be used in digital acoustic systems. The paper proves that from the viewpoint of the important metrological property of such converters i.e. the level of quantization error there is no superiority in performance of A/D converters with higher order modulators over converters with modulator of first order. It was confirmed by a simulation experiment, performed using the MICROCAP circuit simulator (Figs. 7 and 8), where the quantization error levels were compared for modulators of first and second order. Moreover, there is pointed out a certain inconsistency present in numerous papers [2, 4, 5] in which the frequency domain analysis is used to explain noise shaping phenomenon. There is no direct digital filtration possible straight at the sigma-delta modulator output and decimation afterwards. In fact both actions are performed by a single counter, which can be described as both, basically decimator and digital filter (Fig.6).
Źródło:
Pomiary Automatyka Kontrola; 2014, R. 60, nr 2, 2; 94-97
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Switched Current Sigma-Delta Modulator with a New Comparator Structure Designed Based on VHDL-AMS Description
Autorzy:
Śniatała, P
Handkiewicz, A
Naumowicz, M.
Szczęsny, S.
Melosik, M.
Katarzyński, P.
Kropidłowski, M.
Powiązania:
https://bibliotekanauki.pl/articles/227188.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
switched current
VHDL-AMS
sigma-delta modulator
Opis:
The paper presents a VHDL-AMS based approach to the Switched-Current (SI) Sigma-Delta Modulator design. The prototype VHDL-AMS description, with the help of elaborated EDA tools, is automatically translated into the SI realization. Another tool helps the designer to create the layout. The paper also describes a new current mode comparator, which is used in the design. Postlayout simulation results are presented.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 391-396
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of a 3rd order 1.5-bit continuous-time (CT) sigma-delta (ΣΔ) modulator optimized for class D audio power amplifier
Autorzy:
de Melo, J.
Paulino, N.
Powiązania:
https://bibliotekanauki.pl/articles/398039.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
czas ciągły sigma-delta(ΣΔ)
wzmacniacz klasy D
audio
Continuous-Time(CT) Sigma-Delta(ΣΔ)
class D amplifier
Opis:
This paper presents a 3rd order 1.5-bit ΣΔ modulator with distributed feedback and local resonator feedback for a Class D audio amplifier. In order to improve the signal-to-noise-and-distortion ratio (SNDR), without increasing the oversampling ratio (OSR) or the order of the modulator, the modulator uses transmission zeros and 1.5-bit quantization. High level simulations of the modulator architecture show that it has a maximum SNDR value of 81 dB, for a signal bandwidth of 18 kHz and a sampling frequency of 1.2 MHz. An electrical circuit is designed to implement the proposed architecture and the electrical simulations show that it has a maximum SNDR value of 76.1 dB. The influence of the constituting blocks of the circuit in the performance of the modulator is investigated using electrical simulations.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 2; 156-164
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Metrological properties of A/D converters utilizing higher order sigma-delta modulators compared with A/D converters with modulators of first order
Autorzy:
Sidor, T.
Powiązania:
https://bibliotekanauki.pl/articles/221049.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
A/D converters
sigma-delta modulators
quantization errors
Opis:
Time domain analysis is used to determine whether A/D converters that employ higher order sigma-delta modulators, widely used in digital acoustic systems, have superior performance over classical synchronous A/D converters with modulators of first order when taking into account their important metrological property which is the magnitude of the quantization error. It is shown that the quantization errors of delta-sigma A/D converters with higher order modulators are exactly on the same level as for converters with a first order modulator.
Źródło:
Metrology and Measurement Systems; 2014, 21, 1; 39-46
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Noise Transfer Function Design and Optimization for Digital Sigma-Delta Audio DAC
Autorzy:
Lewandowski, M.
Powiązania:
https://bibliotekanauki.pl/articles/177463.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
noise transfer function (NTF)
NTF design
NTF optimization
sigma-delta modulation
sigma-delta audio DAC
psychoacoustic NTF optimization
NTF stability criteria
Opis:
The parameters of sigma-delta audio DAC depend mainly on digital sigma-delta modulator’s features, especially on its noise transfer function (NTF). Many methods of design and optimization of the loop filter’s coefficients in sigma-delta modulators have been proposed so far. These methods enable the designer to get suitable noise transfer functions for specific application. This paper reviews NTF design and optimization methods which are particularly useful in audio applications.
Źródło:
Archives of Acoustics; 2011, 36, 1; 87-108
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Rapid Prototyping of Third-Order Sigma-Delta A/D Converters
Autorzy:
Suszyński, R.
Wawryn, K.
Powiązania:
https://bibliotekanauki.pl/articles/226620.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
sigma-delta converter
A/D converter
FPAA
MASH structure
Opis:
Prototyping ot third-order sigma-delta analog to dogital converters (ΣΔ ADCs) has been presented in the paper. The method is based on implementation of field programmable analog arrays (FPAA) to configure and reconfigure proposed circuits. Three third-order ΣΔ ADC structures have been considered. The circuit characteristics have been measured and then the structure of the converters have been reconfigured tro satisfy input specifications.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 1; 99-104
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Impulsive Sound Detection Directly in Sigma-Delta Domain
Autorzy:
Miranda, I. D. dos S.
Lima, A. C. de C.
Powiązania:
https://bibliotekanauki.pl/articles/176966.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
impulsive signal detection
sigma-delta modulation
discrete cosine transform
Opis:
Recent implementations of Sigma-Delta (ΣΔ) converters have achieved low cost, low power consumption, and high integration while maintaining resolution as high as in Nyquist-rate converters. However, its usage implies demodulating the source signal delivered from ΣΔ modulation to Pulse-Code Modulation (PCM) on a pre-processing stage. This work proposes an algorithm based on Discrete Cosine Transform for impulsive signal detection to be applied directly on a modulated ΣΔ bitstream, targeting to reduce computational cost in acoustic event detection applications such as gunshot recognition systems. From pre-recorded impulsive sounds in ΣΔ format, it has been shown that the new method presents a similar error rate in comparison with traditional energy-based approaches in PCM, meanwhile, it reduces significantly the number of operations per unit time.
Źródło:
Archives of Acoustics; 2017, 42, 2; 255-261
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Rapid design exploration of low pass highly efficient single loop single bit sigma delta (ΣΔ) modulators
Autorzy:
Krishna, S. Vamsee
Reddy, P. Sudhakara
Reddy, S. Chandra Mohan
Powiązania:
https://bibliotekanauki.pl/articles/38699542.pdf
Data publikacji:
2023
Wydawca:
Instytut Podstawowych Problemów Techniki PAN
Tematy:
sigma delta modulator
single loop
time domain
virtual instrument
biomedical application
modulator sigma delta
pojedyncza pętla
dziedzina czasu
instrument wirtualny
zastosowanie biomedyczne
Opis:
A rapid design and verification of sigma delta modulators are presented at the systemlevel with high accuracy and computational efficiency. Sigma delta analog to digital converters showcased an excellent choice for low bandwidth applications from near DC tohigh bandwidth standard 5G applications. The conceptualization of the graphical userinterface (GUI) in the efficient selection of integrator weights has been proposed, whichsolves various tradeoffs between various abstraction levels. The sigma delta modulator of the 5th order is designed and simulated using the proposed design methodology of calculating integrator weights for targeted specifications. The efficiency of design explorationand optimum selection of integrator coefficients has been investigated on single loop architectures. Power and performance of the selected modulator has been verified in the timedomain behavioral simulation. The discrete time circuit technique has been adopted fordesign of distributed feedback, feed forward architectures and comparison of performancemetrics done between selected architectures. A huge design space is computed for the bestdesign parameters that offers ultra-low power and high performance. The proposed virtual instruments supported the methodology for designing delta sigma modulators at thesystem level achieving SNDR of 122 dB over a bandwidth of 5 kHz at a clock frequencyof 1 MHz.
Źródło:
Computer Assisted Methods in Engineering and Science; 2023, 30, 1; 27-39
2299-3649
Pojawia się w:
Computer Assisted Methods in Engineering and Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Evolutionary optimization of Sigma-Delta modulated analog stimulus
Autorzy:
Golonek, T.
Powiązania:
https://bibliotekanauki.pl/articles/397702.pdf
Data publikacji:
2015
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
analog electronic circuits testing
evolutionary optimization
sigma-delta modulation
pulse density modulation
analogowy układ elektroniczny
optymalizacja ewolucyjna
modulacja sigma-delta
modulacja gęstości impulsów
Opis:
This paper proposes the evolutionary technique of the stimulus signal optimization for the analog electronic circuit testing purpose. The obtained signal is coded with Sigma-Delta modulation usage that allows to generate it easily by simple microcontrollers without the necessity of expensive D/A peripherals applying. The signal with the controlled impulses density may be obtained on the external output terminal of the typical timer and finally, it defines the analog signal that can be reconstructed after low pass filtering.
Źródło:
International Journal of Microelectronics and Computer Science; 2015, 6, 4; 130-135
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Sampling Jitter in Audio A/D Converters
Autorzy:
Kulka, Z.
Powiązania:
https://bibliotekanauki.pl/articles/177046.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog-to-digital converter
ADC
successive approximation register (SAR)
sigma-delta ADC
sample-and-hold circuit
DT sigma delta modulator
CT sigma delta modulator
time jitter
aperture jitter
clock jitter
periodic clock jitter
signal-to-noise ratio (SNR)
Opis:
This paper provides an overview of the effects of timing jitter in audio sampling analog-to-digital converters (ADCs), i.e. PCM (conventional or Nyquist sampling) ADCs and sigma-delta (ΣΔ) ADCs. Jitter in a digital audio is often defined as short- term fluctuations of the sampling instants of a digital signal from their ideal positions in time. The influence of the jitter increases particularly with the improvements in both resolution and sampling rate of today’s audio ADCs. At higher frequencies of the input signals the sampling jitter becomes a dominant factor in limiting the ADCs performance in terms of signal-to-noise ratio (SNR) and dynamic range (DR).
Źródło:
Archives of Acoustics; 2011, 36, 4; 831-849
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs
Autorzy:
Abdollahvand, S.
Goes, J.
Paulino, N.
Gomes, L.
Powiązania:
https://bibliotekanauki.pl/articles/397961.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
filtr decymacyjny
filtr wielofazowy
modulator sigma-delta
field-programmable gate array
FPGA
decimation filter
Polyphase Comb filter
sigma-delta modulators
field programmable gate array (FPGA)
Opis:
This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 4; 152-158
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An active power filter based on a hybrid converter topology – Part 1
Autorzy:
Gwóźdź, Michał
Ciepliński, Łukasz
Powiązania:
https://bibliotekanauki.pl/articles/2090725.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
shunt active power filter
pulse width modulation
PWM
sigma-delta modulator
silicon carbide
bocznikowy filtr mocy czynnej
modulacja szerokości impulsu
modulator sigma-delta
węglik krzemu
Opis:
This paper presents a concept of a shunt active power filter, which is able to provide more precise mapping of its input current drawn from a power line in a reference signal, as compared to a typical filter solution. It can be achieved by means of an interconnection of two separate power electronics converters making, as a whole, a controlled current source, which mainly determines the quality of the shunt active filter operation. One of these power devices, the “auxiliary converter”, corrects the total output current, being a sum of output currents of both converters, toward the reference signal. The rated output power of the auxiliary converter is much lower than the output power of the main one, while its frequency response is extended. Thanks to both these properties and the operation of the auxiliary converter in a continuous mode, pulse modulation components in the filter input current are minimized. Benefits of the filter are paid for by a relatively small increase in the complexity and cost of the system. The proposed solution can be especially attractive for devices with higher output power, where, due to dynamic power loss in power switches, a pulse modulation carrier frequency must be lowered, leading to the limitation of the “frequency response” of the converter. The concept of such a system was called the “hybrid converter topology”. In the first part of the paper, the rules of operation of the active filter based on this topology are presented. Also, the results of comparative studies of filter simulation models based on both typical, i.e. single converter, and hybrid converter topologies, are discussed.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 1; e136218, 1--10
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An active power filter based on a hybrid converter topology – Part 1
Autorzy:
Gwóźdź, Michał
Ciepliński, Łukasz
Powiązania:
https://bibliotekanauki.pl/articles/2173586.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
shunt active power filter
pulse width modulation
PWM
sigma-delta modulator
silicon carbide
bocznikowy filtr mocy czynnej
modulacja szerokości impulsu
modulator sigma-delta
węglik krzemu
Opis:
This paper presents a concept of a shunt active power filter, which is able to provide more precise mapping of its input current drawn from a power line in a reference signal, as compared to a typical filter solution. It can be achieved by means of an interconnection of two separate power electronics converters making, as a whole, a controlled current source, which mainly determines the quality of the shunt active filter operation. One of these power devices, the “auxiliary converter”, corrects the total output current, being a sum of output currents of both converters, toward the reference signal. The rated output power of the auxiliary converter is much lower than the output power of the main one, while its frequency response is extended. Thanks to both these properties and the operation of the auxiliary converter in a continuous mode, pulse modulation components in the filter input current are minimized. Benefits of the filter are paid for by a relatively small increase in the complexity and cost of the system. The proposed solution can be especially attractive for devices with higher output power, where, due to dynamic power loss in power switches, a pulse modulation carrier frequency must be lowered, leading to the limitation of the “frequency response” of the converter. The concept of such a system was called the “hybrid converter topology”. In the first part of the paper, the rules of operation of the active filter based on this topology are presented. Also, the results of comparative studies of filter simulation models based on both typical, i.e. single converter, and hybrid converter topologies, are discussed.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 1; art. no. e136218
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł

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