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Wyszukujesz frazę "Intel Xeon" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Feasibility of FPGA to HPC computation migration of plasma impurities diagnostic algorithms
Autorzy:
Linczuk, P.
Krawczyk, R. D.
Zabolotny, W.
Wojenski, A.
Kolasinski, P.
Pozniak, K. T.
Kasprowicz, G.
Chernyshova, M.
Czarski, T.
Powiązania:
https://bibliotekanauki.pl/articles/226512.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
plasma diagnostic
GEM system
feedback loops
Intel Xeon
Intel Xeon Phi
high performance computing HPC
Opis:
We present a feasibility study of fast events parameters estimation algorithms regarding their execution time. It is the first stage of procedure used on data gathered from gas electron multiplier (GEM) detector for diagnostic of plasma impurities. Measured execution times are estimates of achievable times for future and more complex algorithms. The work covers usage of Intel Xeon and Intel Xeon Phi - high-performance computing (HPC) devices as a possible replacement for FPGA with highlighted advantages and disadvantages. Results show that less than 10 ms feedback loop can be obtained with the usage of 25% hardware resources in Intel Xeon or 10% resources in Intel Xeon Phi which leaves space for future increase of algorithms complexity. Moreover, this work contains a simplified overview of basic problems in actual measurement systems for diagnostic of plasma impurities, and emerging trends in developed solutions.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 3; 323-328
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Porting of finite element integration algorithm to Xeon Phi coprocessor-based HPC architectures
Autorzy:
Krużel, Filip
Banaś, Krzysztof
Iacomo, Mauro
Powiązania:
https://bibliotekanauki.pl/articles/38704636.pdf
Data publikacji:
2023
Wydawca:
Instytut Podstawowych Problemów Techniki PAN
Tematy:
CPU
optimization
parallelization
vectorization
Intel Xeon Phi
procesor
optymalizacja
równoległość
wektoryzacja
Opis:
In the present article, we describe the implementation of the finite element numerical integration algorithm for the Xeon Phi coprocessor. The coprocessor was an extension of the many-core specialized unit for calculations, and its performance was comparable with the corresponding GPUs. Its main advantages were the built-in 512-bit vector registers and the ease of transferring existing codes from traditional x86 architectures. In the article, we move the code developed for a standard CPU to the coprocessor. We compareits performance with our OpenCL implementation of the numerical integration algorithm, previously developed for GPUs. The GPU code is tuned to fit into a coprocessor by ourauto-tuning mechanism. Tests included two types of tasks to solve, using two types of approximation and two types of elements. The obtained timing results allow comparing the performance of highly optimized CPU and GPU codes with a Xeon Phi coprocessor performance. This article answers whether such massively parallel architectures perform better using the CPU or GPU programming method. Furthermore, we have compared the Xeon Phi architecture and the latest available Intel’s i9 13900K CPU when writing this article. This comparison determines if the old Xeon Phi architecture remains competitive in today’s computing landscape. Our findings provide valuable insights for selectingthe most suitable hardware for numerical computations and the appropriate algorithmic design.
Źródło:
Computer Assisted Methods in Engineering and Science; 2023, 30, 4; 427-459
2299-3649
Pojawia się w:
Computer Assisted Methods in Engineering and Science
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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