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Wyszukujesz frazę "CMOS analog integrated circuits" wg kryterium: Temat


Wyświetlanie 1-3 z 3
Tytuł:
Versatile low-output-resistance low-voltage current-to-voltage analog converter
Autorzy:
Wojtyna, R.
Powiązania:
https://bibliotekanauki.pl/articles/397867.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
CMOS analog integrated circuits
low-voltage signal processing
current to voltage conversion
transresistor
układy analogowe CMOS
układy scalone CMOS
przetwarzanie sygnałów
konwersja prąd na napięcie
transrezystor
Opis:
The paper presents a simple low-voltage transresistor attractive for on-chip analog-signal-processing. The proposed circuit offers not only an almost rail-to-rail operation and quite good linearity of DC transfer characteristic but also reasonably low value of its output resistance. This enables a voltage mode operation even if the transresistor is loaded by a not necessarily very high loading resistance. The obtained result is due to adding to the transresistor-input-stage a simple rail-to-rail voltage follower. The presented solution is an original proposal of the author. Input stage of the transresistor is built of only 4 MOS transistors and creates a simple quasi-linear current-to-voltage convertor. Output stage of it is built of 9 MOS transistors, plays a role of a very precise atypical voltage follower. In respect of simplicity and headroom, the proposed follower is better than conventional OA-based voltage followers. Preliminary simulation results are in a good agreement with the theory presented.
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 2; 73-78
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions
Autorzy:
Mueller, J. H.
Strache, S.
Busch, L.
Wunderlich, R.
Heinen, S.
Powiązania:
https://bibliotekanauki.pl/articles/226396.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog-digital conversion
analog-digital integrated circuits
calibration
CMOS integrated circuits
mathematical model
MATLAB
mixed analog digital integrated circuits
noise
numerical simulation
prediction methods
Opis:
This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 2; 161-167
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors
Autorzy:
Passos, F.
Fino, M. H.
Moreno, E. R.
Powiązania:
https://bibliotekanauki.pl/articles/226450.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
inductor design
variable width integrated spiral inductor
integrated spiral inductor
CMOS analog circuits
IC designing
RF IC design
Opis:
In this paper a general method for the determination of the series inductance of polygonal tapered inductor s is presented. The value obtained can be integrated into any integrated inductor lumped element model, thus granting the overall characterization of the device and the evaluation of performance parameters such as the quality factor or the resonance frequency. In this work, the inductor is divided into several segments and the corresponding self and mutual inductances are calculated. In the end, results obtained for several working examples are compared against electromagnetic (EM) simulations are performed in order to check the validity of the model for square, hexagonal, octagonal and tapered inductors. The proposed method depends exclusively on the geometric characteristics of the inductor as well as the technological parameters. This allows its straight forward application to any inductor shape or technology.
Źródło:
International Journal of Electronics and Telecommunications; 2014, 60, 1; 73-77
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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