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Wyświetlanie 1-15 z 86
Tytuł:
A 65 nm CMOS Resistorless Current Reference Source with Low Sensitivity to PVT Variations
Autorzy:
Łukaszewicz, M.
Borejko, T.
Pleskacz, W. A.
Powiązania:
https://bibliotekanauki.pl/articles/397920.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
efekt objętościowy
obwody zasilające
napięcie progowe
current reference
65 nm CMOS
body effect
power supply circuits
threshold voltage
Opis:
This paper describes a resistorless current reference source, e.g. for fast communication interfaces. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 59 ppm/°C temperature coefficient over range of -40°C to 125°C. Reference current susceptibility to process parameters variation is ± 2.88%. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -142 dB and -131 dB, respectively.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 4; 119-124
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
Autorzy:
Kushwaha, P.
Chaudhry, A.
Powiązania:
https://bibliotekanauki.pl/articles/308384.pdf
Data publikacji:
2011
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
5T SRAM
65 nm CMOS technology
6T SRAM
7T SRAM
low power SRAM
power reduction technique
Opis:
In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
Źródło:
Journal of Telecommunications and Information Technology; 2011, 4; 124-130
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A High-Efficient Low-Voltage Rectifier for CMOS Technology
Autorzy:
Jendernalik, W.
Jakusz, J.
Blakiewicz, G.
Kłosowski, M.
Powiązania:
https://bibliotekanauki.pl/articles/220356.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS rectifier
high frequency rectifier
wireless power transmission
Opis:
A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages.
Źródło:
Metrology and Measurement Systems; 2016, 23, 2; 261-268
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A MOSFET only, step-up DC DC micro power converter, for solar energy harvesting applications
Autorzy:
Carvalho, C.
Paulino, N.
Powiązania:
https://bibliotekanauki.pl/articles/398057.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
układy CMOS
elektronika
energia zbiorów
układy zarządzania energią
komórki fotowoltaiczne
CMOS circuits
electronics
energy harvesting
power management circuits
PV cells
Opis:
In this paper, a step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitor voltage doubler architecture with MOSFET capacitors, which results in an area approximately eight times smaller than using MiM capacitors for the 0.13 žm CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit uses a phase controller, designed specifically to work with the series of two PV cells, in order to regulate the output voltage to 1.2 V. Electrical simulations of the circuit, together with an equivalent electrical model of a PV cell, show that the circuit can deliver a power of 536.1 žW to the load, while drawing a power of 799.8 žW from two PV cells stacked in series, corresponding to a maximum efficiency of 67%.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 2; 112-119
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Simplified Design Methodology for MOSFET-Only Wideband Mixer
Autorzy:
Ortigueira, E.
Bastos, I.
Oliveira, L. B.
Oliveira, J. P.
Goes, J.
Powiązania:
https://bibliotekanauki.pl/articles/227194.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS mixers
MOSFET-only circuits
Gilbert cell
active mixers
wideband mixers
Opis:
In this paper we present a MOSFET-only implementation of a wideband Gilbert Cell. The circuit uses a commongate topology for a wideband input match, capable to cover the Wireless Medical Telemetry Service (WMTS) frequency bands of 600 MHz and 1.4 GHz. In this circuit the load resistors are replaced by transistors in triode region, to reduce area and cost, and minimize the effects of process and supply variations and mismatches. In addition, we obtain a higher gain for the same DC voltage drop, with a reduced impact on the noise figure (NF). The performance of this topology is compared with that of a conventional mixer with load resistors. Simulation results show that a peak gain of 20.6 dB (about 6 dB improvement) and a NF about of 11 dB for the 600 MHz band. The total power consumption is 3.6 mW from a 1.2 V supply.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 4; 503-509
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Advances in Digitization of Microphones and Loudspeakers
Autorzy:
Kulka, Z.
Powiązania:
https://bibliotekanauki.pl/articles/177402.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
electret condenser microphone
digital microphone
CMOS-MEMS digital microphone
digital microphone array
sigma-delta ADC/DAC
digital loudspeaker
CMOS-MEMS digital loudspeaker
digital loudspeaker array
Opis:
The development of digital microphones and loudspeakers adds new and interesting possibilities of their applications in different fields, extended from industrial, medical to consumer audio markets. One of the rapidly growing field of applications is mobile multimedia, such as mobile phones, digital cameras, laptop and desktop PCs, etc. The advances have also been made in digital audio, particularly in direct digital transduction, so it is now possible to create the all-digital audio recording and reproduction chains potentially having several advantages over existing analog systems.
Źródło:
Archives of Acoustics; 2011, 36, 2; 419-436
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An accurate prediction of high-frequency circuit behaviour
Autorzy:
Yoshitomi, S.
Kimijima, H.
Kojima, K.
Kokatsu, H.
Powiązania:
https://bibliotekanauki.pl/articles/308807.pdf
Data publikacji:
2005
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
electro-magnetic simulation
SPICE
circuit test structure
RF CMOS
EKV2.6-MOS model
spiral inductor
CMOS VCO
Opis:
An accurate way to predict the behaviour of an RF analogue circuit is presented. A lot of effort is required to eliminate the inaccuracies that may generate the deviation between simulation and measurement. Efficient use of computer-aided design and incorporation of as many physical effects as possible overcomes this problem. Improvement of transistor modelling is essential, but there are many other unsolved problems affecting the accuracy of RF analogue circuit modelling. In this paper, the way of selection of accurate transistor model and the extraction of parasitic elements from the physical layout, as well as implementation to the circuit simulation will be presented using two CMOS circuit examples: an amplifier and a voltage controlled oscillator (VCO). New simulation technique, electro-magnetic (EM)-co-simulation is introduced.
Źródło:
Journal of Telecommunications and Information Technology; 2005, 1; 47-62
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analizy symulacyjne układów stymulacyjnych pod kątem wykorzystania w wielokanałowych układach scalonych
Simulation analysis of stimulation circuits for implantable multichannel integrated circuits
Autorzy:
Kmon, P.
Drozd, A.
Powiązania:
https://bibliotekanauki.pl/articles/155529.pdf
Data publikacji:
2013
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
stymulacja elektryczna
układy wielokanałowe
układy ASIC
CMOS
electrical stimulation
multichannel circuits
ASIC
Opis:
W artykule dokonano przeglądu elektronicznych układów stymulacyjnych stosowanych do elektrycznej stymulacji komórek nerwowych. Pod uwagę brane były krytyczne parametry tych bloków w kontekście ich planowanej implementacji w wielokanałowym układzie scalonym. Są to m.in. rozrzuty prądów stymulacyjnych, pobór mocy tych układów, stopień komplikacji układowej czy też zajętość powierzchni krzemu. Przedstawione są podstawowe parametry i wymagania dotyczące układów stymulacyjnych oraz wyniki symulacyjne trzech powszechnie stosowanych architektur zaimplementowanych w technologii CMOS 180nm.
The paper presents a review of stimulation circuits dedicated to multichannel implantable electrical stimulation of large population of neuronal cells. We take into account the main requirements of such circuits, i.e. spread of generated stimulation impulses from channel to channel, power and area consumption and architecture complexity. The paper contains analysis of the main problems that may be encountered while designing current sources able to both generating currents in a broad range and satisfying requirements referring to its output resistance, low output voltage, and uniformity of generated currents. Three most popular architectures of current stimulators are taken into consideration: solution with two independently controlled positive and negative currents and two solutions where one of the currents is generated as the copy of the second one. Simulations were carried out with use of the Cadence environment and the CMOS 180nm process was taken into account. The simulation results followed by the conclusions are presented at the end of the paper.
Źródło:
Pomiary Automatyka Kontrola; 2013, R. 59, nr 3, 3; 243-246
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analogue CMOS ASICs in image processing systems
Autorzy:
Jendernalik, W.
Blakiewicz, G.
Handkiewicz, A.
Melosik, M.
Powiązania:
https://bibliotekanauki.pl/articles/221661.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog CMOS circuits
early vision processing
switched current filters
Opis:
In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.
Źródło:
Metrology and Measurement Systems; 2013, 20, 4; 613-622
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis and design of a MOSFET-only wideband balun LNA
Autorzy:
Bastos, I.
Oliveira, L. B.
Goes, J.
Silva, M.
Powiązania:
https://bibliotekanauki.pl/articles/397861.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
tranzystor polowy MOS-tylko obwody
redukcja hałasu
CMOS LNAs
MOSFET-only circuits
noise cancelling
wideband LNA
Opis:
In this paper we present a MOSFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancellation of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and to minimize the effect of process and supply variations and mismatches. In addition, we obtain a higher gain for the same voltage drop. Thus, the LNA gain is optimized and the noise figure (NF) is reduced. We derive equations for the gain, input matching and NF. The performance of this new topology is compared with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS technology show that we obtain a balun LNA with a peak gain of 20.2 dB (about 2 dB improvement), and a spot NF lower than 2.4 dB. The total power consumption is only 4.8 mW for a bandwidth higher than 6 GHz.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 3; 241-248
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis and design of CMOS coupled multivibrators
Autorzy:
Casaleiro, J.
Lopes, H. F.
Oliveira, L. B.
Filanovsky, I.
Powiązania:
https://bibliotekanauki.pl/articles/397859.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
multiwibrator
CMOS oscillator
multivibrator
quadrature outputs
van der Pol oscillator
WMTS appications
Opis:
In this paper a wideband MOS quadrature oscillator constituted by two multivibrators is presented. Two different forms of coupling, named here as soft and hard, are investigated. Simulations are performed in a 0.13 žm CMOS technology to obtain the tuning range, the synchronization transients, and the influence of mismatches in timing capacitors and charging currents on synchronization. It is found that hard coupling reduces the quadrature error (about 1°, with 5% mismatches in timing capacitors and charging currents) and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling. Either a single multivibrator or coupled multivibrators can be locked to an external synchronizing harmonic frequency, and the locking range is investigated by simulations. The simulations are done for oscillators covering the WTMS frequency bands.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 3; 249-256
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis and verification of integrated circuit thermal parameters
Analiza i weryfikacja parametrów termicznych układu scalonego
Autorzy:
Frankiewicz, M
Gołda, A.
Kos, A.
Powiązania:
https://bibliotekanauki.pl/articles/408531.pdf
Data publikacji:
2014
Wydawca:
Politechnika Lubelska. Wydawnictwo Politechniki Lubelskiej
Tematy:
rezystancja termiczna
pojemność termiczna
termiczna stała czasowa
CMOS
thermal resistance
thermal capacity
thermal time constant
Opis:
The paper describes thermal model of an ASIC designed and fabricated in CMOS 0.7 µm (5 V) technology. The integrated circuit consists of analogue and digital heat sources and some temperature sensors. It has been designed to carry out some thermal tests. During tests thermal resistances, capacities, time constants and convection coefficients for different packages, positions and cooling methods were extracted. The parameters of thermal model were used in simulation to compare results with real-world measurements.
Artykuł opisuje model termiczny układu ASIC zaprojektowanego i sfabrykowanego w technologii CMOS 0,7 µm (5 V). Układ scalony składa się z analogowych i cyfrowych źródeł ciepła oraz czujników temperatury a został zaprojektowany w celu wykonywania testów termicznych. Podczas przeprowadzonych testów zmierzone zostały rezystancja termiczna, pojemność termiczna, termiczna stała czasowa i uogólniony współczynnik konwekcji dla różnych wariantów obudowy, jej położenia i metody chłodzenia. Parametry modelu termicznego zostały użyte w symulacjach w celu porównania wyników z rzeczywistymi pomiarami.
Źródło:
Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska; 2014, 4; 11-15
2083-0157
2391-6761
Pojawia się w:
Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of a Simple Method of CMOS IC Design for Yield Optimization
Autorzy:
Tomaszewski, D.
Yakupov, M.
Powiązania:
https://bibliotekanauki.pl/articles/397989.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
CMOS
projektowanie pod kątem zysku
funkcja gęstości prawdopodobieństwa
dystrybuanta
modelowanie statystyczne
BPV
symulacja SPICE
design centering
design for yield
probability density function
cumulative distribution function
statistical modeling
BPV method
SPICE simulation
Opis:
A simple approach for CMOS integrated circuit (IC) design taking into account a process variability and oriented towards optimization of a parametric yield has been presented. Its concept is based on cumulative distribution functions of random variables representing IC performances subject to process variations. In the method it has been assumed that CMOS process statistical data are expressed in terms of so-called process parameter distributions. Thus the design centering is done via layout parameter tuning. The approach relies on maximizing the probability that random variables corresponding to IC performances remain within the performance boundaries. Also, a methodology for statistical characterization of CMOS process has been briefly described. Finally, the method operation has been illustrated using analytical and SPICE models of CMOS inverter, operational amplifier and ring oscillator.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 3; 81-87
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
Autorzy:
Bieniek, T.
Beck, R. B.
Jakubowski, A.
Głuszko, G.
Konarski, P.
Ćwil, M.
Powiązania:
https://bibliotekanauki.pl/articles/308685.pdf
Data publikacji:
2007
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
CMOS
dual gate oxide
gate stack
oxynitride
plasma implantation
Opis:
The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
Źródło:
Journal of Telecommunications and Information Technology; 2007, 3; 3-8
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 86

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