Temat: 65 nm CMOS - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: A 65 nm CMOS Resistorless Current Reference Source with Low Sensitivity to PVT Variations
Autorzy:: Łukaszewicz, M.
Borejko, T.
Pleskacz, W. A.
Powiązania:: https://bibliotekanauki.pl/articles/397920.pdf
Data publikacji:: 2012
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: efekt objętościowy
obwody zasilające
napięcie progowe
current reference
65 nm CMOS
body effect
power supply circuits
threshold voltage
Opis:: This paper describes a resistorless current reference source, e.g. for fast communication interfaces. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 59 ppm/°C temperature coefficient over range of -40°C to 125°C. Reference current susceptibility to process parameters variation is ± 2.88%. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -142 dB and -131 dB, respectively.
Źródło:: International Journal of Microelectronics and Computer Science; 2012, 3, 4; 119-124
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
Autorzy:: Kushwaha, P.
Chaudhry, A.
Powiązania:: https://bibliotekanauki.pl/articles/308384.pdf
Data publikacji:: 2011
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: 5T SRAM
65 nm CMOS technology
6T SRAM
7T SRAM
low power SRAM
power reduction technique
Opis:: In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
Źródło:: Journal of Telecommunications and Information Technology; 2011, 4; 124-130
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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