Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

English (EN)·Polski (PL)·Yкраїнський (UK)
Przejdź do strony domowej biblioteki Centralna Biblioteka Wojskowa Link otwiera się w nowym oknie Logo biblioteki Prolib Integro - strona głównaCentralna Biblioteka Wojskowa

Wyszukujesz frazę "Zydek, D." wg kryterium: Autor

  Lista filtrów
Wyrównaj
    Wyświetlanie 1-6 z 6
    Tytuł:
    Features Reduction Using Logic Minimization Techniques
    Autorzy:
    Borowik, G.
    Łuba, T.
    Zydek, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/227282.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    machine learning
    knowledge representation
    discernibility function
    logic minimization
    attribute reduction
    complement
    Opis:
    This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 71-76
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance
    Autorzy:
    Zydek, D.
    Chma, G.
    Shawky, A.
    Selvaraj, H.
    Powiązania:
    https://bibliotekanauki.pl/articles/227230.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMP
    PA
    JS
    energy
    assignment
    Opis:
    High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 9-14
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Overlay Multicast Optimization : IBM ILOG CPLEX
    Autorzy:
    Kucharzak, M.
    Zydek, D.
    Poźniak-Koszałka, I.
    Powiązania:
    https://bibliotekanauki.pl/articles/226362.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    overlay multicast
    maximum flows
    linear programming
    mixed-integer programming
    Opis:
    IBM ILOG CPLEX Optimization Studio delivers advanced and complex optimization libraries that solve linear programming (LP) and related problems, e.g., mixed integer. Moreover, the optimization tool provides users with its Academic Research Edition, which is available for teaching and noncommercial research at no-charge. This paper describes the usage of CPLEX C++ API for solving linear problems and, as an exhaustive example, optimization of network flows in overlay multicast is taken into account. Applying continuous and integral variables and implementing various constraints, including equations and inequalities, as well as setting some global parameters of the solver are presented and widely explained.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 4; 381-388
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Problem-Independent Approach to Multiprocessor Dependent Task Scheduling
    Autorzy:
    Król, D.
    Zydek, D.
    Koszałka, L.
    Powiązania:
    https://bibliotekanauki.pl/articles/226364.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    tasks scheduling
    DAG
    genetic algorithm
    tabu search
    makespan
    Opis:
    This paper concerns Directed Acyclic Graph task scheduling on parallel executors. The problem is solved using two new implementations of Tabu Search and genetic algorithm presented in the paper. A new approach to solution coding is also introduced and implemented in both metaheuristics algorithms. Results given by the algorithms are compared to those generated by greedy LPT and SS-FF algorithms; and HAR algorithm. The analysis of the obtained results of multistage simulation experiments confirms the conclusion that the proposed and implemented algorithms are characterized by very good performance and characteristics.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 4; 369-379
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Energy characteristic of a processor allocator and a network-on-chip
    Autorzy:
    Zydek, D.
    Selvaraj, H.
    Borowik, G.
    Łuba, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/907790.pdf
    Data publikacji:
    2011
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    wzmacniacz mocy
    model energetyczny
    przydział procesora
    CMP
    PA
    energy model
    processor allocation
    Opis:
    Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2011, 21, 2; 385-399
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Evaluation Scheme for NoC-based CMP with Integrated Processor Management System
    Autorzy:
    Zydek, D.
    Selvaray, H.
    Koszałka, L.
    Poźniak-Koszałka, I.
    Powiązania:
    https://bibliotekanauki.pl/articles/226964.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    chip multiprocessor
    evaluation system
    PA
    processor allocation
    multiprocessor system
    Network on Chip (NoC)
    Opis:
    With the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 2; 157-167
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-6 z 6

      Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies